Datasheet

R01DS0031EJ0210 Rev.2.10 Page 103 of 111
Jul 31, 2012
M16C/65 Group 5. Electrical Characteristics
Figure 5.31 Timing Diagram
BCLK
CSi
ADi
ALE
RD
Hi-Z
DBi
BHE
Read timing
BCLK
CSi
ADi
ALE
BHE
DBi
Write timing
Hi-Z
Memory Expansion Mode and Microprocessor Mode
(in 1 to 3 waits setting and when accessing external area)
1
V = V = 3V
CC1 CC2
t
d(BCLK-CS)
30ns(max.)
0ns(min.)
t
cyc
t
h(BCLK-AD)
t
d(BCLK-AD)
30ns(max.)
t
d(BCLK-ALE)
25ns(max.)
0ns(min.)
t
h(BCLK-CS)
-4ns(min.)
t
h(BCLK-ALE)
0ns(min.)
t
h(RD-AD)
t
d(BCLK-RD)
30ns(max.)
0ns(min.)
t
h(BCLK-RD)
t
su(DB-RD)
0ns(min.)
t
h(RD-DB)
t
d(BCLK-CS)
30ns(max.)
0ns(min.)
t
h(BCLK-CS)
t
cyc
t
d(BCLK-AD)
30ns(max.)
0ns(min.)
t
h(BCLK-AD)
t
d(BCLK-ALE)
25ns(max.)
-4ns(min.)
t
h(BCLK-ALE)
(0.5 × t -10)ns(min.)
cyc
t
h(WR-AD)
t
d(BCLK-WR)
30ns(max.)
0ns(min.)
t
h(BCLK-WR)
t
d(BCLK-DB)
40ns(max.)
0ns(min.)
t
h(WR-DB)
t
d(DB-WR)
{(n-0.5) × t -40}ns(min.)
cyc
(0.5 × t -10)ns(min.)
cyc
t =
cyc
t
h(BCLK-DB)
n: 1 (when 1 wait)
2 (when 2 waits)
3 (when 3 waits)
Measuring conditions
y V
= V = 3V
CC1 CC2
y Input timing voltage: V = 0.6 V, V = 2.4 V
IL IH
y Output timing voltage: V = 1.5 V, V = 1.5 V
OL OH
f
(BCLK)
{(n+0.5) × t -60}ns(max.)
cyc
t
ac2(RD-DB)
50ns(min.)
WR, WRL,
WRH