Datasheet

R01DS0032EJ0200 Rev.2.00 Page 7 of 88
Feb 07, 2011
M16C/64A Group 1. Overview
1.5 Pin Assignments
Figure 1.4 and Figure 1.5 show pin assignments. Table 1.4 and Table 1.5 list pin names.
Figure 1.4 Pin Assignment for the 100-Pin Package
56 55 54 53 52 51
1
M16C/64A Group
PRQP0100JD-B
(100P6F-A)
(Top view)
2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
VREF
AVSS
VCC1
XIN
XOUT
VSS
RESET
CNVSS
P8_7/XCIN
P8_6/XCOUT
BYTE
P7_4/TA2OUT/W
AVCC
P10_0/AN0
P10_1/AN1
P10_2/AN2
P10_3/AN3
P9_3/DA0/TB3IN/PWM0 P9_4/DA1/TB4IN/PWM1
P9_5/ANEX0/CLK4
P9_6/ANEX1/SOUT4
P9_1/TB1IN/PMC1/SIN3
P9_2/TB2IN/PMC0/SOUT3
P7_2/CLK2/TA1OUT/V
P8_2/INT0
P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN
(1)
P8_3/INT1
P8_5/NMI/SD/CEC
(1)
P9_7/ADTRG/SIN4
P9_0/TB0IN/CLK3
P7_0/TXD2/SDA2/SDAMM/TA0OUT
(1)
P8_4/INT2/ZP
P7_3/CTS2/RTS2/TA1IN/V
P7_5/TA2IN/W
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P5_6/ALE
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
P5_7/RDY/CLKOUT
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P6_0/RTCOUT/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P5_0/WRL/WR
P5_1/WRH/BHE
P1_4/D12 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 VCC2 VSS
P7_6/TA3OUT/TXD5/SDA5
P7_7/TA3IN/CLK5
P8_0/TA4OUT/U/RXD5/SCL5
P8_1/TA4IN/U/CTS5/RTS5
P1_0/CTS6/RTS6/D8 P1_1/CLK6/D9 P1_2/RXD6/SCL6/D10 P1_3/TXD6/SDA6/D11
P4_5/CLK7/CS1
P4_4/CTS7/RTS7/CS0
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets [ ] represent a single functional signal.
They should not be considered as two separate functional signals.
P3_0/A8 [A8/D7] P2_0/AN2_0/A0, [A0/D0], A0 P2_1/AN2_1/A1, [A1/D1], [A1/D0] P2_2/AN2_2/A2, [A2/D2], [A2/D1] P2_3/AN2_3/A3, [A3/D3], [A3/D2] P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3] P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4] P2_7/AN2_7/A7, [A7/D7], [A7/D6]
See Note 3
P2_6/AN2_6/A6, [A6/D6], [A6/D5] P1_5/INT3/IDV/D13 P1_6/INT4/IDW/D14 P1_7/INT5/IDU/D15
P4_6/PWM0/RXD7/SCL7/CS2
P4_7/PWM1/TXD7/SDA7/CS3
VCC2 ports
VCC1 ports