Datasheet

R01DS0032EJ0200 Rev.2.00 Page 68 of 88
Feb 07, 2011
M16C/64A Group 5. Electrical Characteristics
V
CC1
= V
CC2
= 5 V
Switching Characteristics
(V
CC1
= V
CC2
= 5 V, V
SS
= 0 V, at T
opr
= -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.4.3 In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Notes:
1. Calculated according to the BCLK frequency as follows:
2. Calculated according to the BCLK frequency as follows:
n is 2 for 2-wait setting, 3 for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
4. Calculated according to the BCLK frequency as follows:
5. When using multiplex bus, set f
(BCLK)
12.5 MHz or less.
Table 5.37 Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus)
(5)
Symbol Parameter
Measuring
Condition
Standard
Unit
Min. Max.
t
d(BCLK-AD)
Address output delay time
See
Figure 5.14
25 ns
t
h(BCLK-AD)
Address output hold time (in relation to BCLK)
0ns
t
h(RD-AD)
Address output hold time (in relation to RD)
(Note 1) ns
t
h(WR-AD)
Address output hold time (in relation to WR)
(Note 1) ns
t
d(BCLK-CS)
Chip select output delay time
25 ns
t
h(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0ns
t
h(RD-CS)
Chip select output hold time (in relation to RD)
(Note 1) ns
t
h(WR-CS)
Chip select output hold time (in relation to WR)
(Note 1) ns
t
d(BCLK-RD)
RD signal output delay time
25 ns
t
h(BCLK-RD)
RD signal output hold time
0ns
t
d(BCLK-WR)
WR signal output delay time
25 ns
t
h(BCLK-WR)
WR signal output hold time
0ns
t
d(BCLK-DB)
Data output delay time (in relation to BCLK)
40 ns
t
h(BCLK-DB)
Data output hold time (in relation to BCLK)
0ns
t
d(DB-WR)
Data output delay time (in relation to WR)
(Note 2) ns
t
h(WR-DB)
Data output hold time (in relation to WR)
(Note 1) ns
t
d(BCLK-ALE)
ALE signal output delay time (in relation to BCLK)
15 ns
t
h(BCLK-ALE)
ALE signal output hold time (in relation to BCLK)
−4ns
t
d(AD-ALE)
ALE signal output delay time (in relation to Address)
(Note 3) ns
t
h(AD-ALE)
ALE signal output hold time (in relation to Address)
(Note 4) ns
t
d(AD-RD)
RD signal output delay from the end of address
0ns
t
d(AD-WR)
WR signal output delay from the end of address
0ns
t
dz(RD-AD)
Address output floating start time
8ns
0.5 10
9
×
f
BCLK()
----------------------10ns[]–
n 0.5–()10
9
×
f
BCLK()
------------------------------------40ns[]–
0.5 10
9
×
f
BCLK()
----------------------25ns[]–
0.5 10
9
×
f
BCLK()
----------------------15ns[]–