Datasheet

R01DS0032EJ0200 Rev.2.00 Page 42 of 88
Feb 07, 2011
M16C/64A Group 5. Electrical Characteristics
Note:
1. The average output current is the mean value within 100 ms.
Note:
1. The device is operationally guaranteed under these operating conditions.
Figure 5.1 Ripple Waveform
Table 5.3 Recommended Operating Conditions (2/3)
V
CC1
= V
CC2
= 2.7 to 5.5 V at T
opr
= -20°C to 85°C/-40°C to 85°C unless otherwise specified.
Symbol Parameter
Standard
Unit
Min. Typ. Max.
I
OL(sum)
Low peak
output
current
Sum of I
OL(peak)
at P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7
80.0 mA
I
OL(peak)
Low peak
output
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
10.0 mA
I
OL(avg)
Low
average
output
current
(1)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
5.0 mA
f
(XIN)
Main clock input
oscillation frequency
V
CC1
= 2.7 V to 5.5 V 2 20 MHz
f
(XCIN)
Sub clock oscillation frequency 32.768 50 kHz
f
(PLL)
PLL clock oscillation
frequency
V
CC1
= 2.7 V to 5.5 V 10 25 MHz
f
(BCLK)
CPU operation clock 2 25 MHz
t
SU(PLL)
PLL frequency
synthesizer
stabilization wait time
V
CC1
= 5.0 V 2 ms
V
CC1
= 3.0 V 3 ms
Table 5.4 Recommended Operating Conditions (3/3)
(1)
V
CC1
= 2.7 to 5.5 V, V
SS
= 0 V, and T
opr
= -20°C to 85°C/-40°C to 85°C unless otherwise specified.
The ripple voltage must not exceed V
r(VCC1)
and/or dV
r(VCC1)
/dt.
Symbol Parameter
Standard
Unit
Min. Typ. Max.
V
r(VCC1)
Allowable ripple voltage
V
CC1
= 5.0 V
0.5 Vp-p
V
CC1
= 3.0 V
0.3 Vp-p
dV
r(VCC1)
/dt Ripple voltage falling gradient
V
CC1
= 5.0 V
0.3 V/ms
V
CC1
= 3.0 V
0.3 V/ms
V
r( )
V
CC1
V
CC1