Datasheet

R01DS0033EJ0220 Rev.2.20 Page 4 of 115
Nov 01, 2012
M16C/63 Group 1. Overview
Table 1.3 Specifications for the 80-Pin Package (1/2)
Item Function Description
CPU Central processing unit
M16C/60 Series core
(multiplier: 16 bit × 16 bit  32 bit,
multiply and accumulate instruction: 16 bit × 16 bit + 32 bit  32 bit)
• Number of basic instructions: 91
• Minimum instruction execution time:
50.0 ns (f(BCLK) = 20 MHz, VCC1 = 2.7 to 5.5 V)
100.0 ns (f(BCLK) = 10 MHz, VCC1 = 2.1 to below 2.7 V)
200.0 ns (f(BCLK) = 5 MHz, VCC1 = 1.8 V)
• Operating mode: Single-chip
Memory ROM, RAM, data flash See Table 1.5 “Product List”.
Voltage
Detection
Voltage detector
• Power-on reset
• 3 voltage detection points (detection level of voltage detection 0 and 1
selectable)
Clock Clock generator
• 4 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz),
high-speed on-chip oscillator (40 MHz ±10%)
• Oscillation stop detection: Main clock oscillation stop/restart detection
function
• Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16
Sub clock frequency divider circuit: Divide ratio selectable from 1 and 2
• Power saving features: Wait mode, stop mode
• Real-time clock
External Bus
Expansion
Bus memory expansion None
I/O Ports Programmable I/O ports
• CMOS I/O ports: 68 (selectable pull-up resistors)
• N-channel open drain ports: 3
Interrupts
• Interrupt vectors: 70
• External interrupt inputs: 14 (NMI, INT × 5, key input × 8)
• Interrupt priority levels: 7
Watchdog Timer
15-bit timer × 1 (with prescaler)
Automatic reset start function selectable
DMA DMAC
• 4 channels, cycle steal mode
• Trigger sources: 43
• Transfer modes: 2 (single transfer, repeat transfer)