Datasheet

R01DS0033EJ0220 Rev.2.20 Page 75 of 115
Nov 01, 2012
M16C/63 Group 5. Electrical Characteristics
Figure 5.16 Timing Diagram
BCLK
CSi
ADi
ALE
RD
25ns(max.)
0ns(min.)
Hi-Z
DBi
0ns(min.)
BHE
Read timing
Memory Expansion Mode and Microprocessor Mode
(in no wait state setting)
25ns(max.) 0ns(min.)
BCLK
CSi
ADi
ALE
BHE
40ns(max.)
0ns(min.)
DBi
Write timing
Hi-Z
1
V = V = 5V
CC1 CC2
15ns(max.)
t
h(BCLK-CS)
t
cyc
t
h(BCLK-AD)
0ns(min.)
t
d(BCLK-AD)
t
d(BCLK-ALE)
-4ns(min.)
t
h(RD-AD)
0ns(min.)
t
d(BCLK-RD)
t
h(BCLK-RD)
0ns(min.)
t
ac1(RD-DB)
t
su(DB-RD)
t
h(RD-DB)
t
h(BCLK-ALE)
25ns(max.)
t
d(BCLK-CS)
25ns(max.)
t
d(BCLK-CS)
25ns(max.)
0ns(min.)
t
h(BCLK-CS)
t
cyc
25ns(max.)
0ns(min.)
15ns(max.)
t
d(BCLK-ALE)
-4ns(min.)
t
h(BCLK-ALE)
t
d(BCLK-AD)
t
h(BCLK-AD)
t
h(WR-AD)
t
d(BCLK-WR)
t
h(BCLK-WR)
t
d(BCLK-DB)
t
h(BCLK-DB)
t
d(DB-WR)
t
h(WR-DB)
t =
cyc
Measuring conditions
y V
= V = 5V
CC1 CC2
y Input timing voltage: V = 0.8 V, V = 2.0 V
IL IH
y Output timing voltage: V = 0.4 V, V = 2.4 V
OL OH
f
(BCLK)
40ns(min.)
(0.5 × t -40)ns(min.)
cyc
(0.5 × t - 10)ns(min.)
cyc
(0.5 × t -10)ns(min.)
cyc
(0.5 × t -45)ns(max.)
cyc
WR, WRL,
WRH