Datasheet

R8C/M11A Group, R8C/M12A Group 2. Central Processing Unit (CPU)
R01DS0010EJ0200 Rev.2.00 Page 11 of 45
May 31, 2012
2. Central Processing Unit (CPU)
Figure 2.1 shows the 13 CPU Registers. The registers, R0, R1, R2, R3, A0, A1, and FB form a single register bank.
The CPU has two register banks.
Figure 2.1 CPU Registers
The higher 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
Interrupt table register
Data registers
(1)
Address registers
(1)
Frame base register
(1)
User stack pointer
Interrupt stack pointer
Static base register
Program counter
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bits
Processor interrupt priority level
Reserved bit
Note:
1. These registers form a single register bank.
The CPU has two register banks.
Flag register
R3
R2
b31 b0b15
FB
R2
R3
A0
A1
R0H (R0 high-order byte)
R1H (R1 high-order byte)
R0L (R0 low-order byte)
R1L (R1 low-order byte)
INTBH
b19 b0
INTBL
b15
PC
b19 b0
b15 b0
USP
ISP
SB
b15 b0
FLG
b15 b0b8 b7
CDZSBOIUIPL
b8 b7