Datasheet

R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 2. Central Processing Unit (CPU)
R01DS0011EJ0101 Rev.1.01 Page 29 of 102
Oct 28, 2011
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register banks.
Figure 2.1 CPU Registers
R2
b31
b15 b8b7
b0
Data registers
(1)
Address registers
(1)
R3
R0H (high-order of R0)
R2
R3
A0
A1
INTBH
b15b19
b0
INTBL
FB
Frame base register
(1)
The 4 high-order bits of INTB are INTBH and
the 16 low-order bits of INTB are INTBL.
Interrupt table register
b19
b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
C
IPL
DZSBOIU
b15
b0
b15
b0
b15
b0
b8
b7
Note:
1. These registers configure a register bank.
There are two sets of register banks.
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)