Datasheet
R8C/36C Group 1. Overview
R01DS0018EJ0110 Rev.1.10 Page 8 of 59
Nov 02, 2010
1.4 Pin Assignment
Figure 1.3 shows Pin Assignment (Top View). Tables 1.5 and 1.6 outline the Pin Name Information by Pin Number.
Figure 1.3 Pin Assignment (Top View)
43 42 41 40 39 38 37 36
24
17
18
19
20
21
22
23
1 34567891011122
35 34 33
13 14 15 16
25
26
27
28
29
30
31
32
4445464748
R8C/36C Group
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
PTQP0064LB-A
(Top view)
P0_7/AN0/DA1(/TRCIOC)
P0_6/AN1/DA0(/TRCIOD)
P0_5/AN2(/TRCIOB)
P0_4/AN3/TREO(/TRCIOB)
P0_3/AN4(/CLK1/TRCIOB)
P0_2/AN5(/RXD1/TRCIOA/TRCTRG)
P0_1/AN6(/TXD1/TRCIOA/TRCTRG)
P0_0/AN7(/TRCIOA/TRCTRG)
P6_4(/RXD1)
P6_3(/TXD1)
P6_2(/CLK1)
P6_1
P6_0(/TREO)
P5_7(/TRGIOB)
P5_6(/TRAO/TRGIOA)
P3_2(/INT1/INT2/TRAIO/TRGCLKB)
P8_4(/TRFO11)
P8_5(/TRFO12)
P8_6
P3_1(/TRBO)
P3_6(/INT1)
P2_0(/INT1/TRCIOB/TRDIOA0/TRDCLK)
P2_1(/TRCIOC/TRDIOC0)
P2_2(/TRCIOD/TRDIOB0)
P2_3(/TRDIOD0)
P2_4(/TRDIOA1)
P2_5(/TRDIOB1)
P2_6(/TRDIOC1)
P2_7(/TRDIOD1)
P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)
P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC)
P3_5/SCL/SSCK(/CLK2/TRCIOD)
P3_0(/TRAO/TRGCLKA)
P4_2/VREF
MODE
P4_3(/XCIN)
P4_4(/XCOUT)
RESET
P4_7/XOUT
VSS/AVSS
P4_6/XIN
VCC/AVCC
P5_4(/TRCIOD)
P5_3(/TRCIOC)
P5_2(/TRCIOB)
P5_1(/TRCIOA/TRCTRG)
P5_0(/TRCCLK)
P3_7/SDA/SSO/TRAO(/RXD2/SCL2/TXD2/SDA2)
P1_0/AN8/KI0(/TRCIOD)
P1_1/AN9/KI1(/TRCIOA/TRCTRG)
P1_2/AN10/KI2(/TRCIOB)
P1_3/AN11/KI3/TRBO(/TRCIOC)
P1_4(/TXD0/TRCCLK)
P1_5(/INT1/RXD0/TRAIO)
P1_6/IVREF1(/CLK0)
P1_7/IVCMP1/INT1(/TRAIO)
P4_5/ADTRG/INT0(/RXD2/SCL2)
P6_5/INT4(/CLK1/CLK2/TRCIOB)
P6_6/INT2(/TXD2/SDA2/TRCIOC)
P6_7(/INT3/TRCIOD)
P8_0(/TRFO00)
P8_1(/TRFO01)
P8_2(/TRFO02)
P8_3(/TRFI/TRFO10)
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. P4_2 is an input-only pin.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
60
59
58
57
56
55
54
53
52
51
50
49
61
62
63
64