Datasheet

R8C/2E Group, R8C/2F Group 1. Overview
Rev.1.00 Dec 14, 2007 Page 8 of 39
REJ03B0222-0100
1.3 Block Diagram
Figure 1.3 shows a Block Diagram.
Figure 1.3 Block Diagram
Watchdog timer
(15 bits)
R8C/Tiny Series CPU core
Memory
ROM
(1)
RAM
(2)
Multiplier
R0H R0L
R1H
R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O ports
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
System clock
generation circuit
XIN-XOUT
High-speed on-chip oscillator
Low-Speed on-chip oscillator
Timers
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RE (8 bits × 1)
A/D converter
(10 bits
× 12 channels)
UART or
clock synchronous serial I/O
(8 bits × 1)
Comparator
(× 2)
LIN module
8
Port P0
8
Port P1
6
Port P3
1 3
Port P4
2
Port P5
Peripheral functions
D/A converter
(8 bits
× 2)