Datasheet

A - 2
REVISION HISTORY R8C/24 Group, R8C/25 Group Datasheet
0.10 Feb 24, 2005 1 to 3
5, 6
Pin type changed: 48-pin(under consideration) → 52-pin.
5 to 7 Package type revised: 48-pin LQFP
(under consideration) →
PLQP0052JA-A
8 Table 1.5 TCLK added, VREF revised.
9 Table 1.6 revised.
13, 14 Figures 3.1 and 3.2 part number revised.
15 Tabel 4.1 revised:
- 000Fh: 000XXXXXb
→ 00011111b
- 0023h: FR0
→ FRA0
- 0024h: FR1
→ FRA1
- 0025h: FR2
→ FRA2
- 0031h: Voltage Detection A Register 1, VC1
→ Voltage Detection Register 1, VCA1
- 0032h: Voltage Detection A Register 2, VC2
→ Voltage Detection Register 2, VCA2
17 Tabel 4.3 Register name and the value after reset at 00B8h to 00BFh
revised; NOTE2 added.
19 Tabel 4.5 revised:
- 0107h: LINSR
→ LINST
- 0137h to 013Fh: Register symbol revised
20 Tabel 4.6 revised:
- 0140h to 015Fh: Register symbol revised
- 0158h, 0159h:
Timer RD General Register → Timer RD General Register
A1
0.20 Mar 8, 2005 2, 3
8
Tables 1.1, 1.2 and 1.5 revised: “main clock” → “XIN clock”; “sub clock”
→ “XCIN clock”
15 - 0023h to 0025h: 40MHz On-Chip Oscillator Control Register
→ High-Speed On-Chip Oscillator Control Register
0.30 Sep 01, 2005 2, 3 Table 1.1 R8C/24 Group Performance, Table 1.2 R8C/25 Group
Performance
• Serial Interface revised:
- Serial Interface: 2 channels Clock synchronous serial I/O, UART
- Clock Synchronous Serial Interface: 1 channel
I
2
C bus Interface
(1)
, Clock synchronous serial I/O with chip select
4 Figure 1.1 Block Diagram
• UART or Clock Synchronous Serial Interface: “(8 bits × 1 channel)”
→
“(8 bits × 2 channels)” revised
• UART (8 bits × 1 channel) deleted
5, 6 Table 1.3 Product Information of R8C/24 Group, Table 1.4 Product
Information of R8C/25 Group
“Flash Memory Version”
→ “N Version” revised
Rev. Date
Description
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