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To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (51 pages)

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To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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R8C/1A Group, R8C/1B Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. REJ03B0144-0140 Rev.1.40 Dec 08, 2006 Overview These MCUs are fabricated using the high-performance silicon gate CMOS process, embedding the R8C/ Tiny Series CPU core, and is packaged in a 20-pin molded-plastic LSSOP, SDIP or a 28-pin plastic moldedHWQFN. It implements sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed.
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R8C/1A Group, R8C/1B Group 1.2 1. Overview Performance Overview Table 1.1 outlines the Functions and Specifications for R8C/1A Group and Table 1.2 outlines the Functions and Specifications for R8C/1B Group. Table 1.1 CPU Functions and Specifications for R8C/1A Group Item Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Ports Specification 89 instructions 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.
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R8C/1A Group, R8C/1B Group Table 1.2 CPU 1. Overview Functions and Specifications for R8C/1B Group Item Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Ports Specification 89 instructions 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) Single-chip 1 Mbyte See Table 1.
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R8C/1A Group, R8C/1B Group 1.3 1. Overview Block Diagram Figure 1.1 shows a Block Diagram.
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R8C/1A Group, R8C/1B Group 1.4 1. Overview Product Information Table 1.3 lists Product Information for R8C/1A Group and Table 1.4 lists Product Information for R8C/1B Group. Table 1.3 Product Information for R8C/1A Group Type No.
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R8C/1A Group, R8C/1B Group Type No. 1.
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R8C/1A Group, R8C/1B Group Table 1.4 1. Overview Product Information for R8C/1B Group Type No.
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R8C/1A Group, R8C/1B Group Type No. 1.
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R8C/1A Group, R8C/1B Group 1.5 1. Overview Pin Assignments Figure 1.4 shows Pin Assignments for PLSP0020JB-A Package (Top View), Figure 1.5 shows Pin Assignments for PRDP0020BA-A Package (Top View) and Figure 1.6 shows Pin Assignments for PWQN0028KA-B Package (Top View).
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R8C/1A Group, R8C/1B Group 1. Overview PIN assignments (top view) 1 20 P3_4/SCS/SDA/CMP1_1 P3_7/CNTR0/SSO/TXD1 2 19 P3_3/TCIN/INT3/SSI00/CMP1_0 RESET 3 18 P1_0/KI0/AN8/CMP0_0 XOUT/P4_7(1) 4 17 P1_1/KI1/AN9/CMP0_1 VSS/AVSS 5 16 P4_2/VREF XIN/P4_6 6 15 P1_2/KI2/AN10/CMP0_2 VCC/AVCC 7 14 P1_3/KI3/AN11/TZOUT MODE 8 13 P1_4/TXD0 P4_5/INT0/RXD1 9 12 P1_5/RXD0/CNTR01/INT11 10 11 P1_6/CLK0/SSI01 P1_7/CNTR00/INT10 R8C/1A Group R8C/1B Group P3_5/SSCK/SCL/CMP1_2 NOTE: 1.
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R8C/1A Group, R8C/1B Group 1.
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R8C/1A Group, R8C/1B Group 1.6 1. Overview Pin Functions Table 1.5 lists Pin Functions, Table 1.6 lists Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages and Table 1.7 lists Pin Name Information by Pin Number of PWQN0028KAB Package. Table 1.5 Pin Functions Type Symbol I/O Type Description Power Supply Input VCC, VSS I Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
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R8C/1A Group, R8C/1B Group Table 1.6 Pin Number Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages Control Pin 1 2 3 4 5 6 7 8 9 1.
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R8C/1A Group, R8C/1B Group Table 1.7 Pin Number 1 2 3 4 5 6 7 8 9 10 1.
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R8C/1A Group, R8C/1B Group 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank.
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R8C/1A Group, R8C/1B Group 2.1 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32bit data register (R2R0). R3R1 is analogous to R2R0. 2.
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R8C/1A Group, R8C/1B Group 2.8.7 2. Central Processing Unit (CPU) Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
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R8C/1A Group, R8C/1B Group 3. 3. Memory Memory 3.1 R8C/1A Group Figure 3.1 is a Memory Map of R8C/1A Group. The R8C/1A Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine.
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R8C/1A Group, R8C/1B Group 3.2 3. Memory R8C/1B Group Figure 3.2 is a Memory Map of R8C/1B Group. The R8C/1B Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine.
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R8C/1A Group, R8C/1B Group 4. 4. Special Function Registers (SFRs) Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.4 list the special function registers. Table 4.
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R8C/1A Group, R8C/1B Group Table 4.2 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 4.
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R8C/1A Group, R8C/1B Group Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh 4.
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R8C/1A Group, R8C/1B Group Table 4.4 Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 4.
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R8C/1A Group, R8C/1B Group 5. 5. Electrical Characteristics Electrical Characteristics Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr = -20°C to 105°C ). Table 5.1 Absolute Maximum Ratings Rated Value Unit VCC Symbol Supply voltage Parameter VCC = AVCC Condition -0.3 to 6.5 V AVCC Analog supply voltage VCC = AVCC -0.3 to 6.5 V V VI Input voltage -0.3 to VCC+0.3 VO Output voltage -0.3 to VCC+0.
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R8C/1A Group, R8C/1B Group Table 5.3 5. Electrical Characteristics A/D Converter Characteristics Symbol Parameter − Resolution − Absolute accuracy Rladder Resistor ladder tconv Conversion time Conditions Standard Min. Typ. Max. Unit Vref = VCC − − 10 Bits 10-bit mode φAD = 10 MHz, Vref = VCC = 5.0 V − − ±3 LSB 8-bit mode φAD = 10 MHz, Vref = VCC = 5.0 V − − ±2 LSB 10-bit mode φAD = 10 MHz, Vref = VCC = 3.3 V(3) − − ±5 LSB 8-bit mode φAD = 10 MHz, Vref = VCC = 3.
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R8C/1A Group, R8C/1B Group Table 5.4 Flash Memory (Program ROM) Electrical Characteristics Symbol − 5. Electrical Characteristics Parameter Program/erase endurance(2) Conditions Standard Unit Min. Typ. Max. R8C/1A Group 100(3) − − times R8C/1B Group 1,000(3) − − times µs − Byte program time − 50 400 − Block erase time − 0.
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R8C/1A Group, R8C/1B Group Table 5.5 5. Electrical Characteristics Flash Memory (Data flash Block A, Block B) Electrical Characteristics Symbol Parameter Conditions Standard Min. Typ. Max. Unit 10,000(3) − − times Byte program time (Program/erase endurance ≤ 1,000 times) − 50 400 µs − Byte program time (Program/erase endurance > 1,000 times) − 65 − µs − Block erase time (Program/erase endurance ≤ 1,000 times) − 0.
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R8C/1A Group, R8C/1B Group 5. Electrical Characteristics Suspend request (maskable interrupt request) FMR46 Clockdependent time Fixed time (97 µs) Access restart td(SR-SUS) Figure 5.2 Table 5.
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R8C/1A Group, R8C/1B Group Table 5.8 5. Electrical Characteristics Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset) Symbol Parameter Condition Standard Min. Power-on reset valid voltage Vpor2 tw(Vpor2-Vdet1) Supply voltage rising time when power-on reset is deasserted(1) Unit Typ. Max. -20°C ≤ Topr ≤ 85°C − − Vdet1 V -20°C ≤ Topr ≤ 85°C, tw(por2) ≥ 0s(3) − − 100 ms NOTES: 1. This condition is not applicable when using with Vcc ≥ 1.0 V. 2.
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R8C/1A Group, R8C/1B Group Table 5.10 5. Electrical Characteristics High-Speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter Condition Standard Min. Typ. Max. Unit − High-speed on-chip oscillator frequency when the reset is deasserted VCC = 5.0 V, Topr = 25 °C − 8 − MHz − High-speed on-chip oscillator frequency temperature • supply voltage dependence(2) 0 to +60 °C/5 V ± 5 %(3) 7.76 − 8.24 MHz -20 to +85 °C/2.7 to 5.5 V(3) 7.68 − 8.
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R8C/1A Group, R8C/1B Group Table 5.12 5. Electrical Characteristics Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1) Symbol Parameter Conditions Standard Min. Typ. Max. Unit tSUCYC SSCK clock cycle time 4 − − tCYC(2) tHI SSCK clock “H” width 0.4 − 0.6 tSUCYC tLO SSCK clock “L” width tRISE SSCK clock rising time 0.4 − 0.
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R8C/1A Group, R8C/1B Group 5.
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R8C/1A Group, R8C/1B Group 5.
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R8C/1A Group, R8C/1B Group 5. Electrical Characteristics tHI VIH or VOH SSCK VIH or VOH tLO tSUCYC SSO (output) tOD SSI (input) tSU Figure 5.6 tH I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode) Rev.1.
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R8C/1A Group, R8C/1B Group Table 5.13 5. Electrical Characteristics Timing Requirements of I2C bus Interface (1) Symbol Parameter Condition tSCL SCL input cycle time tSCLH SCL input “H” width tSCLL SCL input “L” width tsf tSP SCL, SDA input fall time SCL, SDA input spike pulse rejection time tBUF Standard Typ. (2) − 12tCYC+600 (2) − 3tCYC+300 Min. Max.
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R8C/1A Group, R8C/1B Group Table 5.14 Electrical Characteristics (1) [VCC = 5 V] Symbol VOH 5. Electrical Characteristics IOH = -1 mA Standard Min. Typ. VCC − 2.0 − VCC − 0.3 − VCC − 2.0 − Max. VCC VCC VCC IOH = -500 µA VCC − 2.0 − VCC V − − − − IOL = 15 mA − − 2.0 0.45 2.0 V V V IOL = 5 mA − − 2.0 V IOL = 200 µA − − 0.45 V IOL = 1 mA − − 2.0 V IOL = 500 µA − − 2.0 V INT0, INT1, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RXD0 0.2 − 1.0 V RESET 0.2 − 2.
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R8C/1A Group, R8C/1B Group Table 5.15 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (2) [Vcc = 5 V] (Topr = -40 to 85 °C, unless otherwise specified.) Parameter Condition Power supply current High-speed (VCC = 3.3 to 5.5 V) mode Single-chip mode, output pins are open, other pins are VSS, A/D converter is stopped Mediumspeed mode High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Wait mode Wait mode Stop mode Rev.1.
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R8C/1A Group, R8C/1B Group 5. Electrical Characteristics Timing Requirements (Unless otherwise specified: VCC = 5 V, VSS = 0 V at Ta = 25 °C) [ VCC = 5 V ] Table 5.16 XIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) Standard Min. Max. 50 − 25 − 25 − Parameter XIN input cycle time XIN input “H” width XIN input “L” width Unit ns ns ns VCC = 5 V tc(XIN) tWH(XIN) XIN input tWL(XIN) Figure 5.8 Table 5.
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R8C/1A Group, R8C/1B Group Table 5.19 5. Electrical Characteristics Serial Interface Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 200 − 100 − 100 − − 50 0 − 50 − 90 − Parameter CLKi input cycle time CLKi input “H” width CLKi input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Unit ns ns ns ns ns ns ns i = 0 or 1 VCC = 5 V tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 1 Figure 5.
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R8C/1A Group, R8C/1B Group Table 5.21 Electrical Characteristics (3) [VCC = 3V] Symbol VOH VOL 5. Electrical Characteristics Parameter Output “H” voltage Output “L” voltage Except XOUT XOUT Except P1_0 to P1_3, XOUT P1_0 to P1_3 XOUT VT+-VT- Hysteresis IIH IIL RPULLUP RfXIN fRING-S VRAM RESET Input “H” current Input “L” current Pull-up resistance Feedback resistance XIN Low-speed on-chip oscillator frequency RAM hold voltage IOH = -0.1 mA Standard Min. Typ. VCC − 0.5 − VCC − 0.5 − Max.
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R8C/1A Group, R8C/1B Group Table 5.22 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (4) [Vcc = 3 V] (Topr = -40 to 85 °C, unless otherwise specified.) Parameter Condition Power supply current High-speed (VCC = 2.7 to 3.3 V) mode Single-chip mode, output pins are open, other pins are VSS, A/D converter is stopped Mediumspeed mode High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Wait mode Wait mode Stop mode Rev.1.
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R8C/1A Group, R8C/1B Group 5. Electrical Characteristics Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Ta = 25 °C) [VCC = 3 V] Table 5.23 XIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) Standard Min. Max. 100 − 40 − 40 − Parameter XIN input cycle time XIN input “H” width XIN input “L” width Unit ns ns ns VCC = 3 V tc(XIN) tWH(XIN) XIN input tWL(XIN) Figure 5.13 Table 5.
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R8C/1A Group, R8C/1B Group Table 5.26 5. Electrical Characteristics Serial Interface Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max.
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R8C/1A Group, R8C/1B Group Package Dimensions Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JB-A Previous Code 20P2F-A 11 *1 E 20 HE MASS[Typ.] 0.1g NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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R8C/1A Group, R8C/1B Group JEITA Package Code P-HWQFN28-5x5-0.50 Package Dimensions RENESAS Code PWQN0028KA-B *1 Previous Code 28PJW-B MASS[Typ.] 0.05g D 15 21 21 15 22 14 14 22 E1 *2 E D2 8 28 Lp 28 8 7 7 1 e bp 1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. x y Rev.1.40 Dec 08, 2006 REJ03B0144-0140 A1 F Page 45 of 45 Detail F A A2 Reference Symbol D E A2 A A1 bp e Lp x y D2 E1 Dimension in Millimeters Min Nom Max 4.9 5.0 5.1 4.9 5.0 5.1 0.75 0.
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REVISION HISTORY REVISION HISTORY Description Rev. Date 0.10 Feb 18, 2005 − 0.20 Jun 01, 2005 2, 3 0.30 Jul 04, 2005 R8C/1A Group, R8C/1B Group Datasheet R8C/1A Group, R8C/1B Group Datasheet Page Summary First Edition issued Tables 1.1, 1.2: Item name changed 9 Table 1.5: Timer C’s Pin name revised, Reference Voltage Input Description revised 16 Table 4.1 the value after reset revised; 0009h address “XXXXXX00b” → “00h”, 000Ah address “00XXX000b” → “00h”, 001Eh address “XXXXX000b” → “00h”.
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REVISION HISTORY Rev. Date 1.00 Sep 01, 2005 1.10 1.20 1.30 Dec 16, 2005 Mar 31, 2006 Oct 03, 2006 R8C/1A Group, R8C/1B Group Datasheet Description Page Summary 18 Table 4.
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REVISION HISTORY Rev. Date 1.30 Oct 03, 2006 1.40 Dec 08, 2006 R8C/1A Group, R8C/1B Group Datasheet Description Page 1 Summary 1.1 “portable equipment” added 2, 3 Table 1.1, Table 1.2; Specification Interrupts: “Internal: 9 sources” → “Internal: 11 sources” 24 Table 5.2; Parameter: System clock added 45 Package Dimensions; PWQN0028KA-B revised 20 Table 4.1; 000Fh: After reset “000XXXXXb” → “00X11111b” 24 Table 19.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use.