Datasheet
R8C/11 Group 2. Central Processing Unit (CPU)
Rev.1.60 Jan 27, 2006 page 7 of 26
REJ03B0034-0160
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. Two sets of register banks are provided.
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0
can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.
The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit
data register (R2R0). The same applies to R3R1 as R2R0.
D
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a
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(
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A
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(
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(
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Interrupt stack pointer
Static base register
Flag register
N
O
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S
:
1
.
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R0H (high-order of R0)
b
1
5
b
8
b7 b
0
R
3
I
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B
H
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S
P
ISP
SB
CDZSBOIU
I
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L
R0L (low-order of R0)
R1H (high-order of R1)
R1L (low-order of R1)
R
2
b
3
1
R3
R2
A1
A0
F
B
b
1
9
I
N
T
B
L
b
1
5
b
0
PC
b19
b
0
b
1
5
b
0
F
L
G
b15 b0
b
1
5
b
0
b7 b
8
Reserved bit
Carry flag
D
e
b
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f
l
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Z
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l
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Sign flag
Register bank select flag
O
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R
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b
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Processor interrupt priority level
T
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4
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1
6
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B
L
.
Figure 2.1 CPU Register