Datasheet

RL78/L12
CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
R01UH0330EJ0200 Rev.2.00 949
Dec 13, 2013
(2) I
2
C fast mode
(T
A = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCLA0 clock frequency fSCL
Fast mode:
f
CLK ≥ 3.5 MHz
2.7 V ≤ EV
DD ≤ 5.5 V 0 400 kHz
2.4 V ≤ EVDD ≤ 5.5 V 0 400
Setup time of restart
condition
t
SU:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.6 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0.6
Hold time
Note 1
tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.6 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0.6
Hold time when SCLA0
= “L”
t
LOW 2.7 V ≤ EVDD ≤ 5.5 V 1.3 μ s
2.4 V ≤ EVDD ≤ 5.5 V 1.3
Hold time when SCLA0
= “H”
t
HIGH 2.7 V ≤ EVDD ≤ 5.5 V 0.6 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0.6
Data setup time
(reception)
t
SU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 100 ns
2.4 V ≤ EVDD ≤ 5.5 V 100
Data hold time
(transmission)
Note 2
t
HD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 0.9 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0 0.9
Setup time of stop
condition
t
SU:STO 2.7 V ≤ EVDD ≤ 5.5 V 0.6 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0.6
Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 1.3 μ s
2.4 V ≤ EVDD ≤ 5.5 V 1.3
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of t
HD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode: C
b = 320 pF, Rb = 1.1 kΩ