Datasheet

RL78/L12
CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
R01UH0330EJ0200 Rev.2.00 930
Dec 13, 2013
31.4 AC Characteristics
31.4.1 Basic operation
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle (minimum
instruction execution time)
TCY Main
system
clock (f
MAIN)
operation
HS (high-speed
main) mode
2.7 V ≤ V DD ≤ 5.5 V 0.04167 1 μ s
2.4 V ≤ V DD < 2.7 V 0.0625 1 μ s
Subsystem clock (fSUB)
operation
2.4 V ≤ V DD ≤ 5.5 V 28.5 30.5 31.3 μ s
In the self
programming
mode
HS (high-speed
main) mode
2.7 V ≤ V DD ≤ 5.5 V 0.04167 1 μ s
2.4 V ≤ V DD < 2.7 V 0.0625 1 μ s
External system clock frequency fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz
fEXS 32 35 kHz
External system clock input high-
level width, low-level width
tEXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns
2.4 V ≤ VDD < 2.7 V 30 ns
tEXHS,
t
EXLS
13.7
μ s
TI00 to TI07 input high-level width,
low-level width
tTIH,
t
TIL
1/f
MCK+10 ns
TO00 to TO07 output frequency fTO
HS (high-speed
main) mode
4.0 V ≤ EVDD ≤ 5.5 V 16 MHz
2.7 V ≤ EVDD < 4.0 V 8 MHz
2.4 V ≤ EVDD < 2.7 V 4 MHz
PCLBUZ0, PCLBUZ1 output
frequency
fPCL HS (high-speed
main) mode
4.0 V ≤ EVDD ≤ 5.5 V 16 MHz
2.7 V ≤ EVDD < 4.0 V 8 MHz
2.4 V ≤ EVDD < 2.7 V 4 MHz
Interrupt input high-level width,
low-level width
tINTH,
t
INTL
INTP0 2.4 V ≤ V
DD ≤ 5.5 V 1 μ s
INTP1 to INTP7 2.4 V ≤ EVDD ≤ 5.5 V 1 μ s
Key interrupt input low-level width tKR KR0 to KR3 2.4 V ≤ EVDD ≤ 5.5 V 250 ns
RESET low-level width tRSL 10 μ s
Remark f
MCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n).
n: Channel number (n = 0 to 7))