Datasheet

RL78/L12 CHAPTER 24 REGULATOR
R01UH0330EJ0200 Rev.2.00 796
Dec 13, 2013
CHAPTER 24 REGULATOR
24.1 Regulator Overview
The RL78/L12 contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the
regulator output voltage, connect the REGC pin to V
SS via a capacitor (0.47 to 1 μ F). Also, use a capacitor with good
characteristics, since it is used to stabilize internal voltage.
REGC
V
SS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
The regulator output voltage, see Table 24-1.
Table 24-1. Regulator Output Voltage Conditions
Mode Output Voltage Condition
LV (low voltage main) mode 1.8 V -
LS (low-speed main) mode
HS (high-speed main) mode 1.8 V In STOP mode
When both the high-speed system clock (fMX) and the high-speed on-chip
oscillator clock (f
IH) are stopped during CPU operation with the subsystem clock
(f
XT)
When both the high-speed system clock (fMX) and the high-speed on-chip
oscillator clock (f
IH) are stopped during the HALT mode when the CPU operation
with the subsystem clock (f
XT) has been set
2.1 V
Other than above (include during OCD mode)
Note
Note When it shifts to the subsystem clock operation or STOP mode during the on-chip debugging, the regulator output
voltage is kept at 2.1 V (not decline to 1.8 V).