Datasheet

RL78/L12 CHAPTER 23 SAFETY FUNCTIONS
R01UH0330EJ0200 Rev.2.00 783
Dec 13, 2013
23.3.3 RAM parity error detection function
The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data
in the RL78/L12’s RAM. By using this RAM parity error detection function, the parity bit is appended when data is written,
and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity error
occurs.
23.3.3.1 RAM parity error control register (RPECTL)
This register is used to control parity error generation check bit and reset generation due to parity errors.
The RPECTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 23-7. Format of RAM Parity Error Control Register (RPECTL)
Address: F00F5H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 <0>
RPECTL RPERDIS 0 0 0 0 0 0 RPEF
RPERDIS Parity error reset mask flag
0 Enable parity error resets.
1 Disable parity error resets.
RPEF Parity error status flag
0 No parity error has occurred.
1 A parity error has occurred.
Caution The parity bit is appended when data is written, and the parity is checked when the data is
read.
Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize
RAM areas where data access is to proceed before reading data.
The RL78’s CPU executes look-ahead due to the pipeline operation, the CPU might read an
uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity
error.
Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the
RAM area + 10 bytes when instructions are fetched from RAM areas.
Remarks 1. The parity error reset is enabled by default (RPERDIS = 0).
2. Even if the parity error reset is disabled (RPERDIS = 1), the RPEF flag will be set (1) if a parity
error occurs. If parity error resets are enabled (RPERDIS = 0) with RPEF set to 1, a parity error
reset is generated when the RPERDIS bit is cleared to 0.
3. The RPEF flag in the RPECTL register is set (1) when the RAM parity error occurs and cleared
(0) by writing 0 to it or by any reset source. When RPEF = 1, the value is retained even if RAM
for which no parity error has occurred is read.
4. The general registers are not included for RAM parity error detection.
<R>
<R>