Datasheet

RL78/L12 CHAPTER 21 POWER-ON-RESET CIRCUIT
R01UH0330EJ0200 Rev.2.00 757
Dec 13, 2013
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
and Voltage Detector (2/3)
(2) LVD interrupt & reset mode (option byte 000C1: LVIMDS1, LVIMDS0 = 1, 0)
Note 3
Supply voltage (V DD )
V
LVDH
V LVDL
Lower limit voltage for guaranteed operation
V
POR = 1.51 V (TYP.)
V
PDR = 1.50 V (TYP.)
0 V
High-speed on-chip
oscillator clock (f
IH )
High-speedsystem
clock (f
MX )
(when X1 oscillation
is selected)
CPU Operation stops
Internal reset signal
INTLVI
Voltage stabilization wait + POR reset processing time
1.64 ms (TYP.), 3.10 ms (MAX.) 1.64 ms (TYP.), 3.10 ms (MAX.)
Note 4
LVD reset processing time
Wait for oscillation
accuracy stabilization
Starting oscillation is specified by software
Note 2
Note 1
Normal operation (high-speed
on-chip oscillator clock)
Reset period
(oscillation stop)
Starting oscillation is specified by software
Note 2
Normal operation (high-speed
on-chip oscillator clock)
Note 4
LVD reset processing time
Operation stops
Voltage stabilization wait + POR reset processing time
Wait for oscillation
accuracy stabilization
Note 1
Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-
chip oscillator clock.
2. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected
as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC)
to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for
confirmation of the lapse of the stabilization time.
3. After the first interrupt request signal (INTLVI) is generated, the LVIL and LVIMD bits of the voltage
detection level register (LVIS) are automatically set to 1. After INTLVI is generated, the initial settings
should be made by software after the required save processing if the supply voltage might return to the
high voltage detection level (V
LVDH) or higher without falling below the low voltage detection level (VLVDL).
4. The time until normal operation starts includes the following LVD reset processing time after the LVD
detection level (V
LVDH) is reached as well as the voltage stabilization wait + POR reset processing time after
the V
POR (1.51 V, typ.) is reached.
LVD reset processing time: 0 ms to 0.0701 ms (max.)
Remark V
LVDH, VLVDL: LVD detection voltage
V
POR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
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