Datasheet

RL78/L12 CHAPTER 19 STANDBY FUNCTION
R01UH0330EJ0200 Rev.2.00 738
Dec 13, 2013
Figure 19-2. HALT Mode Release by Reset (2/2)
(3) When subsystem clock is used as CPU clock
HALT
instruction
Reset signal
Subsystem clock
(XT1 oscillation)
Normal operation
(subsystem clock)
HALT mode
Reset
period
Normal operation mode
(high-speed on-chip
oscillator clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Oscillation
stopped
Oscillation stabilization time
(check by using OSTC register)
Note
Starting XT1 oscillation is
specified by software.
Note For the reset processing time, see CHAPTER 20 RESET FUNCTION.
For the reset processing time of the power-on-reset circuit (POR) and voltage detector (LVD), see
CHAPTER 21 POWER-ON-RESET CIRCUIT.
19.3.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the main system clock.
Cautions 1. Because the interrupt request signal is used to clear the STOP mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the STOP mode is
immediately cleared if set. Thus, when a STOP instruction is executed in this situation, the
system returns to its normal operating mode as soon as the wait time set by using the
oscillation stabilization time select register (OSTS) has elapsed. Note that the operating current
during this period is the same as in the HALT mode because the clock is not stopped.
2. When using CSI00, UART0, or the A/D converter in the SNOOZE mode, set up serial standby
control register 0 (SSC0) and A/D converter mode register 2 (ADM2) before switching to the
STOP mode. For details, see 12.3 Registers Controlling Serial Array Unit and 11.3 Registers
Used in A/D Converter.
The operating statuses in the STOP mode are shown below.