Datasheet
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS
R01UH0330EJ0200 Rev.2.00 706
Dec 13, 2013
Table 17-2. Flags Corresponding to Interrupt Request Sources (2/3)
Interrupt
Source
Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag
64-pin
52-pin
48-pin
44-pin
32-pin
Register Register Register
INTDMA0 DMAIF0 IF0H DMAMK0 MK0H DMAPR00, DMAPR10 PR00H,
PR10H
√ √ √ √ √
INTDMA1 DMAIF1 DMAMK1 DMAPR01, DMAPR11
√ √ √ √ √
INTST0
Note 1
STIF0
Note 1
STMK0
Note 1
STPR00, STPR10
Note 1
√ √ √ √ √
INTCSI00
Note 1
CSIIF00
Note 1
CSIMK00
Note 1
CSIPR000, CSIPR100
Note 1
√ √ √ √ √
INTSR0
Note 2
SRIF0
Note 2
SRMK0
Note 2
SRPR00, SRPR10
Note 2
√ √ √ √ √
INTCSI01
Note 2
CSIIF01
Note 2
CSIMK01
Note 2
CSIPR001, CSIPR101
Note 2
√ √ √ √ √
INTSRE0
Note 3
SREIF0
Note 3
SREMK0
Note 3
SREPR00, SREPR10
Note 3
√ √ √ √ √
INTTM01H
Note 3
TMIF01H
Note 3
TMMK01H
Note 3
TMPR001H, TMPR101H
Note 3
√ √ √ √ √
INTTM00 TMIF00 TMMK00 TMPR000, TMPR100
√ √ √ √ √
INTTM03H TMIF03H IF1L TMMK03H MK1L
TMPR003H, TMPR103H PR01L,
PR11L
√ √ √ √ √
INTIICA0 IICAIF0 IICAMK0 IICAPR00, IICAPR10
√ √ √ √ √
INTTM01 TMIF01 TMMK01 TMPR001, TMPR101
√ √ √ √ √
INTTM02 TMIF02 TMMK02 TMPR002, TMPR102
√ √ √ √ √
INTTM03 TMIF03 TMMK03 TMPR003, TMPR103
√ √ √ √ √
INTAD ADIF ADMK ADPR0, ADPR1
√ √ √ √ √
INTRTC RTCIF RTCMK RTCPR0, RTCPR1
√ √ √ √ √
INTIT ITIF ITMK ITPR0, ITPR1
√ √ √ √ √
Notes 1. If one of the interrupt sources INTST0 and INTCSI00 is generated, bit 2 of the IF0H register is set to 1. Bit 2
of the MK0H, PR00H, and PR10H registers supports these two interrupt sources.
2. If one of the interrupt sources INTSR0 and INTCSI01 is generated, bit 3 of the IF0H register is set to 1. Bit
3 of the MK0H, PR00H, and PR10H registers supports these two interrupt sources.
3. Do not use a UART0 reception error interrupt and an interrupt of channel 1 of TAU0 (at higher 8-bit timer
operation) at the same time because they share flags for the interrupt request sources. If the UART0
reception error interrupt is not used (EOC01 = 0), UART0 and channel 1 of TAU0 (at higher 8-bit timer
operation) can be used at the same time. If one of the interrupt sources INTSRE0 and INTTM01H is
generated, bit 7 of the IF0H register is set to 1. Bit 7 of the MK0H, PR00H, and PR10H registers supports
these two interrupt sources.
Remark √: Mounted
<R>