Datasheet

RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER
R01UH0330EJ0200 Rev.2.00 618
Dec 13, 2013
14.3.7 LCD input switch control register (ISCLCD)
Input to the schmitt trigger buffer must be invalid until the CAPL/P126, CAPH/P127, and V
L3/P125 pins are set to
operate as LCD function pins in order to prevent through-current from entering.
This register is set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets ISCLCD to 00H.
Figure 14-8. Format of LCD Input Switch Control Register (ISCLCD)
Address: F0308H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ISCLCD 0 0 0 0 0 0 ISCVL3 ISCCAP
ISCVL3 VL3/P125 pin Schmitt trigger buffer control
0 Input invalid
1 Input valid
ISCCAP CAPL/P126, CAPH/P127 pins Schmitt trigger buffer control
0 Input invalid
1 Input valid
Cautions 1. If ISCVL3 = 0, set the corresponding port registers as follows:
PU125 bit of PU12 register = 0, P125 bit of P12 register = 0
2. If ISCCAP = 0, set the corresponding port registers as follows:
PU127 bit of PU12 register = 0, P127 bit of P12 register = 0
PU126 bit of PU12 register = 0, P126 bit of P12 register = 0
(a) Operation of ports that alternately function as V
L3, CAPL, and CAPH pins
The functions of the V
L3/P125, CAPL/P126, and CAPH/P127 pins can be selected by using the LCD input
switch control register (ISCLCD), LCD mode register 0 (LCDM0), and port mode register 12 (PM12).
• V
L3/P125
Table 14-5. Settings of V
L3/P125 Pin Function
Bias Setting
(LBAS1 and LBAS0 Bits of
LCDM0 Register )
ISCVL3 Bit of
ISCLCD Register
PM125 Bit of
PM12 Register
Pin Function Initial Status
Other than 1/4 bias method
(LBAS1, LBAS0 = 00 or 01)
0 1 Digital input ineffective mode
√
1 0 Digital output mode
−
1 1 Digital input mode
−
1/4 bias method
(LBAS1, LBAS0 = 10)
0 1 VL3 function mode
−
Other than above Setting prohibited