Datasheet

RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER
R01UH0330EJ0200 Rev.2.00 616
Dec 13, 2013
Figure 14-6. Format of LCD Clock Control Register 0 (LCDC0) (2/2)
Address: FFF42H
After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
LCDC0 0 0 LCDC05 LCDC04 LCDC03 LCDC02 LCDC01 LCDC00
(2/2)
LCDC05 LCDC04 LCDC03 LCDC02 LCDC01 LCDC00 LCD clock (LCDCL)
0
1 0 0 0 1 fMAIN/2
8
0
1 0 0 1 0 fMAIN/2
9
0
1 0 0 1 1 fMAIN/2
10
0
1 0 1 0 0 fMAIN/2
11
0
1 0 1 0 1 fMAIN/2
12
0
1 0 1 1 0 fMAIN/2
13
0
1 0 1 1 1 fMAIN/2
14
0
1 1 0 0 0 fMAIN/2
15
0
1 1 0 0 1 fMAIN/2
16
0
1 1 0 1 0 fMAIN/2
17
0
1 1 0 1 1 fMAIN/2
18
1 0 1 0 1 1 fMAIN/2
19
Other than above Setting prohibited
Cautions 1. Do not set LCDC0 when the SCOC bit of the LCDM1 register is 1.
2. Be sure to set bits 6 and 7 to “0”.
3. When the internal voltage boosting method and the capacitor split method are specified, set
the LCD clock (LCDCL) as follows. For details, see Table 14-4 Combinations of Display
Waveform, Time Slices, and Bias Method and Frame Frequency
• If f
SUB is selected, set the clock to a frequency no greater than 512 Hz.
• If f
IL is selected, set the clock to a frequency no greater than 235 Hz.
Remark f
MAIN: Main system clock frequency
f
SUB: Subsystem clock frequency
f
IL: Low-speed on-chip oscillator clock frequency
<R>
<R>