Datasheet

RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER
R01UH0330EJ0200 Rev.2.00 615
Dec 13, 2013
14.3.5 LCD clock control register 0 (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
This register is set by using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDC0 to 00H.
Figure 14-6. Format of LCD Clock Control Register 0 (LCDC0) (1/2)
Address: FFF42H
After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
LCDC0 0 0 LCDC05 LCDC04 LCDC03 LCDC02 LCDC01 LCDC00
(1/2)
LCDC05 LCDC04 LCDC03 LCDC02 LCDC01 LCDC00 LCD clock (LCDCL)
0 0 0 0 0 1 fSUB/2
2
or fIL/2
2 Note
0 0 0 0 1 0 fSUB/2
3
or fIL/2
3 Note
0 0 0 0 1 1 fSUB/2
4
or fIL/2
4 Note
0 0 0 1 0 0 fSUB/2
5
or fIL/2
5 Note
0 0 0 1 0 1 fSUB/2
6
or fIL/2
6 Note
0 0 0 1 1 0 fSUB/2
7
or fIL/2
7 Note
0 0 0 1 1 1 fSUB/2
8
or fIL/2
8 Note
0 0 1 0 0 0 fSUB/2
9
or fIL/2
9 Note
0 0 1 0 0 1 fSUB/2
10
Cautions 1. Be sure to set bits 6 and 7 to “0”.
2. Set the frame frequency in a range from 32 Hz to 128 Hz (24 Hz to 128 Hz when f
IL is selected).
And set the LCD clock (LCDCL) to no more than 512 Hz (no more than 235 Hz when f
IL is
selected) when the internal voltage boosting method, and the capacitor split method have been
specified.
3. Do not set LCDC0 when the SCOC bit of the LCDM1 register is 1.
(Remark is listed on the next page.)