Datasheet

RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER
R01UH0330EJ0200 Rev.2.00 612
Dec 13, 2013
14.3.3 LCD mode register 1 (LCDM1)
LCDM1 enables or disables display operation, voltage boost circuit operation, and capacitor split circuit operation, and
specifies the display data area and the
low voltage mode.
LCDM1 is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LCDM1 to 00H.
Figure 14-4. Format of LCD Mode Register 1 (LCDM1) (1/2)
Address: FFF41H After reset
: 00H R/W
Symbol
<7> <6> <5> <4> <3> 2 1 <0>
LCDM1 LCDON SCOC VLCON BLON LCDSEL 0 0 LCDVLM
SCOC LCDON LCD display enable/disable
When normal liquid crystal waveform (waveform A or B) is output
0 0 Output ground level to segment/common pin
0 1
1 0 Display off (all segment outputs are deselected.)
1 1 Display on
VLCON Voltage boost circuit or capacitor split circuit operation enable/disable
0 Stops voltage boost circuit or capacitor split circuit operation
1
Note 1
Enables voltage boost circuit or capacitor split circuit operation
BLON
Note 2
LCDSEL Display data area control
0 0 Displaying an A-pattern area data (lower four bits of LCD display data register)
0 1 Displaying a B-pattern area data (higher four bits of LCD display data register)
1 0 Alternately displaying A-pattern and B-pattern area data (blinking display corresponding
to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))
1 1
Notes 1. Setting is prohibited when External resistance division method.
2. When f
IL is selected as the LCD source clock (fLCD), be sure to set the BLON bit to “0”.
(Cautions are listed on the next page.)
<R>
<R>