Datasheet

RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER
R01UH0330EJ0200 Rev.2.00 606
Dec 13, 2013
Table 14-2. Maximum Number of Pixels (5/5)
(e) 64-pin products
Drive Waveform for
LCD Driver
LCD Driver Voltage
Generator
Bias Mode Number of
Time Slices
Maximum Number of Pixels
Waveform A External resistance
division
−
Static 39 (39 segment signals, 1 common signal)
1/2 2 78 (39 segment signals, 2 common signals)
3 117 (39 segment signals, 3 common signals)
1/3 3
4 156 (39 segment signals, 4 common signals)
1/4 8 280 (35 segment signals, 8 common signals)
Internal voltage
boosting
1/3 3 117 (39 segment signals, 3 common signals)
4 156 (39 segment signals, 4 common signals)
1/4 8 280 (35 segment signals, 8 common signals)
Capacitor split
1/3 3 117 (39 segment signals, 3 common signals)
4 156 (39 segment signals, 4 common signals)
Waveform B External resistance
division, internal
voltage boosting
1/3 4
1/4 8 280 (35 segment signals, 8 common signals)
Capacitor split
1/3 4 156 (39 segment signals, 4 common signals)
14.2 Configuration of LCD Controller/Driver
The LCD controller/driver consists of the following hardware.
Table 14-3. Configuration of LCD Controller/Driver
Item Configuration
Control registers Peripheral enable register 0 (PER0)
LCD mode register 0 (LCDM0)
LCD mode register 1 (LCDM1)
Subsystem clock supply mode control register (OSMC)
LCD clock control register 0 (LCDC0)
LCD boost level control register (VLCD)
LCD input switch control register (ISCLCD)
LCD port function registers 0 to 4 (PFSEG0 to PFSEG4)
Port mode registers 1, 3 to 7, 12, 14 (PM1, PM3 to PM7, PM12, PM14)
<R>
<R>