Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 499
Dec 13, 2013
Remarks 1. <1> to <12> in the figure correspond to <1> to <12> in Figure 12-88 Timing Chart of SNOOZE
Mode Operation (EOCm1 = 0, SSECm = 0/1) and Figure 12-89 Timing Chart of SNOOZE Mode
Operation (EOCm1 = 1, SSECm = 0).
2. m = 0; q = 0
(3) SNOOZE mode operation (EOCm1 = 1, SSECm = 1: Error interrupt (INTSREq) generation is stopped)
Because EOCm1 = 1 and SSECm = 1, an error interrupt (INTSREq) is not generated when a communication error
occurs.
Figure 12-91. Timing Chart of SNOOZE Mode Operation
(EOCm1 = 1, SSECm = 1)
L
<1>
<2>
<3>
<5> <6>
<7>
<6>
<9>
<4>
P
P
SP SPST
<7>,
<8>
<5>
ST
SS01
SE01
SWC0
SSEC0
SDR01
INTSR0
INTSRE0
TSF01
ST01
RxD0
pin
<10>
<11>
CPU operation status
Normal operation
STOP mode
SNOOZE mode
STOP mode
SNOOZE mode
Normal operation
Receive data 1
Receive data 2
Receive data 2
Receive data 1
Shift operation
Shift operation
Data reception
Data reception
Shift
register 01
Clock request signal
(internal signal)
Read
Note
Note Read the received data when SWCm = 1.
Cautions 1. Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
finishes, set the STm1 bit to 1 (clear the SEm1 bit and stop the operation).
After the receive operation completes, also clear the SWCm bit to 0 (SNOOZE mode release).
2. If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the
PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated.
Therefore, when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1 flag
before setting the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or
SDRm1[8:0] (9 bits).
Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 12-92 Flowchart of SNOOZE Mode
Operation (EOCm1 = 1, SSECm = 1).
2. m = 0; q = 0
<R>