Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 498
Dec 13, 2013
Figure 12-90. Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0)
Setting start
Does TSFmn = 0 on all
channels?
No
Yes
Writing 1 to the STmn bit
→ SEmn = 0
Setting SSCm register
(SWCm = 1, SSECm = 0)
Entered the STOP mode
Writing 1 to the SS mn bit
→ SEm1 = 1
The operation of all channels is also stopped to switch to the
STOP mode.
SNOOZE mode setting
f
CLK supplied to the SAU is stopped.
<1>
<2>
<3>
<4>
<5>
<7>
Channel 1 is specified for UART reception.
(EOCmn: Enable error interrupt.)
<6>
<9>
<8>
<10>
<11>
<12>
The mode switches from SNOOZE to normal
operation.
Communication wait status
SAU default setting
Clear interrupt requ est flag (XXIF), reset interrupt mask (XXMK)
and set interrupt enab le (IE = 1).
Enab le interrupt
RxDq edge detected
(Entered the SNOOZE mode)
Clock supply
(UART receive operation)
Transfer end interrupt (INTSRq) or
error interrupt (INTSREq) generated
Normal operation
Normal operation
STOP mode
SNOOZE mode
Writing 1 to the STm1 bit
Clear the SWCm bit to 0
Reset SNOOZE mode setting.
To operation stop status (SEm1 = 0)
INTSRq
Reading receive data from
the SDRmn[7:0] bits (RXDq
register) (8 bits) or the
SDRmn[8:0] bits (9 bits)
Writing 1 to the STm1 bit
Clear the SWCm bit to 0
INTSREq
Error process ing
Cha nge to the UART
reception baud rate in
normal operation
Writing 1 to the SS mn bit
Normal operation
Change to the UART
reception baud rate in
normal operation
Set the SPSmregister and bits 15 to 9 in the
SDRm1 register.
Writing 1 to the SSmn bit
To communication wait status (SEmn = 1)
Normal operation
Reading receive data from
the SDRmn[7:0] bits (RXDq
register) (8 bits) or the
SDRmn[8:0] bits (9 bits)
(Remarks are listed on the next page.)
<R>