Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 450
Dec 13, 2013
12.5.5 Slave reception
Slave reception is that the RL78 microcontroller receives data from another device in the state of a transfer clock being
input from another device.
3-Wire Serial I/O CSI00 CSI01
Target channel Channel 0 Channel 1
Pins used SCK00, SI00 SCK01, SI01
Interrupt INTCSI00 INTCSI01
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate Max. fMCK/6 [Hz]
Notes 1, 2
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data input starts from the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Non-reverse
• CKPmn = 1: Reverse
Data direction MSB or LSB first
Notes 1. Because the external serial clock input to the SCK00, and SCK01 pins is sampled internally and used, the
fastest transfer rate is f
MCK/6 [Hz].
2. Use this operation within a range that satisfies the conditions above and the peripheral functions
characteristics in the electrical specifications (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: T
A
= -40 to +85°C) and CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)).
Remarks 1. f
MCK: Operation clock frequency of target channel
fSCK: Serial clock frequency
2. m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01
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