Datasheet

RL78/L12 CHAPTER 11 A/D CONVERTER
R01UH0330EJ0200 Rev.2.00 379
Dec 13, 2013
Figure 11-39. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A/D conversion
ADCR
ADIF
ANIn ANIn ANIm ANIm
ANIn ANIn ANIm ANIm
ADS rewrite
(start of ANIm conversion)
ADIF is set but ANIm conversion
has not ended.
(8) Conversion results just after A/D conversion start
In software trigger mode and hardware trigger no-wait mode, if the ADCE bit is set to 1 and then the ADCS bit is set
to 1 before 1.0
μ s elapses, the A/D conversion value immediately after A/D conversion starts might not satisfy the
ratings. In this case, take measures such as polling the A/D conversion end interrupt request signal (INTAD) and
discarding the first conversion result.
(9) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), A/D port configuration register (ADPC), and port mode control register (PMC), the contents of the
ADCR and ADCRH registers may become undefined. Read the conversion result following conversion completion
before writing to the ADM0, ADS, ADPC, or PMC register. Using a timing other than the above may cause an
incorrect conversion result to be read.