Datasheet

RL78/L12 CHAPTER 11 A/D CONVERTER
R01UH0330EJ0200 Rev.2.00 345
Dec 13, 2013
Table 11-3. A/D Conversion Time Selection (2/4)
(2) When there is no stabilization wait time
Note 1
Low-voltage mode 1, 2 (software trigger mode/hardware trigger no-wait mode)
A/D Converter Mode Register 0
(ADM0)
Mode Conversion
Clock (fAD)
Number of
Conversion
Clock
Cycles
Note 8
Conversion
Time
Conversion Time Selection
1.6 V ≤ VDD ≤ 5.5 V Note 2 Note 3 Note 4
FR2 FR1 FR0 LV1 LV0 fCLK =
1 MHz
fCLK =
4 MHz
fCLK =
8 MHz
fCLK =
16 MHz
fCLK =
24 MHz
0 0 0 1 0
Low-
voltage 1
f
CLK/64 19 fAD
(number
of
sampling
clock
cycles:
7 f
AD)
1216/f
CLK
Setting
prohibited
Setting
prohibited
Setting
prohibited
76
μ s 50.6667 μ s
0 0 1 fCLK/32 608/fCLK 76 μ s 38 μ s 25.3333 μ s
0 1 0 fCLK/16 304/fCLK 76 μ s 38 μ s 19 μ s 12.6667 μ s
0 1 1 fCLK/8 152/fCLK 38 μ s
Note 7
19 μ s 9.5 μ s
Note 6
6.3333 μ s
1 0 0 fCLK/6 114/fCLK
28.5
μ
s
Note 7
14.25
μ
s
Note 6
7.125
μ
s
Note 6
4.75
μ
s
1 0 1 fCLK/5 95/fCLK
95
μ
s 23.75
μ
s
Note 7
11.875
μ
s
Note 6
5.938
μ
s
Note 6
3.9587
μ
s
1 1 0 fCLK/4 76/fCLK
76
μ
s 19
μ
s
Note 7
9.5
μ
s
Note 6
4.75
μ
s
Note 6
3.1667
μ
s
Note 5
1 1 1 fCLK/2 38/fCLK
38
μ
s
Note 7
9.5
μ
s
Note 6
4.75
μ
s
Note 6
2.375
μ
s
Note 5
Setting
prohibited
0 0 0 1 1
Low-
voltage 2
fCLK/64 17 fAD
(number
of
sampling
clock
cycles:
5 f
AD)
1088/f
CLK
Setting
prohibited
Setting
prohibited
Setting
prohibited
68
μ
s 45.3333
μ
s
0 0 1 fCLK/32 544/fCLK 68 μ s 34 μ s 22.6667 μ s
0 1 0 fCLK/16 272/fCLK 68 μ s 34 μ s 17 μ s 11.3333 μ s
0 1 1 fCLK/8 136/fCLK 34 μ s
Note 7
17 μ s 8.5 μ s
Note 6
5.6667 μ s
1 0 0 fCLK/6 102/fCLK
25.5
μ
s
Note 7
12.75
μ
s
Note 6
6.375
μ
s
Note 6
4.25
μ
s
1 0 1 fCLK/5 85/fCLK
85
μ
s 21.25
μ
s
Note 7
10.625
μ
s
Note 6
5.3125
μ
s
Note 6
3.5417
μ
s
1 1 0 fCLK/4 68/fCLK
68
μ
s 17
μ
s
Note 7
8.5
μ
s
Note 6
4.25
μ
s
Note 6
2.8333
μ
s
Note 5
1 1 1 fCLK/2 34/fCLK
34
μ
s
Note 7
8.5
μ
s
Note 6
4.25
μ
s
Note 6
2.125
μ
s
Note 5
Setting
prohibited
Notes 1. This mode is prohibited when using the temperature sensors.
2. 1.8 V ≤ V
DD ≤ 5.5 V
3. 2.4 V ≤ V
DD ≤ 5.5 V
4. 2.7 V ≤ V
DD ≤ 5.5 V
5. Setting prohibited when VDD < 3.6 V.
6. Setting prohibited when V
DD < 2.7 V.
7. Setting prohibited when V
DD< 1.8 V.
8. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
selected, the values are shorter by two cycles of the conversion clock (f
AD).
Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV)
described in 30.6.1 A/D converter characteristics or 31.6.1 A/D converter characteristics.
2. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, make sure that
conversion has stopped (ADCS = 0, ADCE = 0).
3. The above conversion time does not include conversion state time. Conversion state time add in
the first conversion. Select conversion time, taking clock frequency errors into consideration.
Remark f
CLK: CPU/peripheral hardware clock frequency
<R>
<R>