Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 257
Dec 13, 2013
Figure 6-67. Example of Set Contents of Registers to Delay Counter (2/2)
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0
0: Sets master channel output mode.
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)