Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 229
Dec 13, 2013
6.7 Timer Input (TImn) Control
6.7.1 TImn input circuit configuration
A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller.
Enable the noise filter for the pin in need of noise removal. The following shows the configuration of the input circuit.
Figure 6-43. Input Circuit Configuration
CCSmn
Timer
controller
Count clock
selection
Trigger
selection
f
TCLK
fMCK
Interrupt signal from master channel
TImn pin
Noise
filter
TNFENmn STSmn2 to
STSmn0
CISmn1,
CISmn0
Edge
detection
6.7.2 Noise filter
When the noise filter is disabled, the input signal is only synchronized with the operating clock (f
MCK) for channel n.
When the noise filter is enabled, after synchronization with the operating clock (fMCK) for channel n, whether the signal
keeps the same value for two clock cycles is detected. The following shows differences in waveforms output from the
noise filter between when the noise filter is enabled and disabled.
Figure 6-44. Sampling Waveforms through TImn Input Pin with Noise Filter Enabled and Disabled
TImn pin
Operating clock (f
MCK)
Noise filter disabled
Noise filter enabled
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