Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT

R01UH0330EJ0200 Rev.2.00 228

Dec 13, 2013

Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer

(INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin.

Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)

6.6.5 Timer Interrupt and TOmn Pin Output at Operation Start

In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to

generate a timer interrupt at count start.

When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation.

In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled.

Figures 6-41 and 6-42 show operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.

Figure 6-41. When MDmn0 is set to 1

TCRmn

TEmn

TOmn

INTTMmn

Count operation start

When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a toggle

operation.

Figure 6-42. When MDmn0 is set to 0