Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 186
Dec 13, 2013
6.3.1 Peripheral enable register 0 (PER0)
This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit is used, be sure to set bit 0 (TAU0EN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-10. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> 3 <2> 1 <0>
PER0 RTCEN 0 ADCEN IICA0EN 0 SAU0EN 0 TAU0EN
TAU0EN Control of timer array unit input clock
0
Stops supply of input clock.
• SFR used by the timer array unit cannot be written.
• The timer array unit is in the reset status.
1
Supplies input clock.
• SFR used by the timer array unit can be read/written.
Cautions 1. When setting the timer array unit, be sure to set the following registers first while the
TAU0EN bit is set to 1. If TAU0EN = 0, the values of the registers which control the timer
array unit are cleared to their initial values and writing to them is ignored (except for the
timer input select register 0 (TIS0), timer output select register (TOS), input switch
control register (ISC), noise filter enable register 1 (NFEN1), port mode control registers
1, 4, 14 (PMC1, PMC4, PMC14), port mode registers 1, 3 to 5, 14 (PM1, PM3 to PM5,
PM14), and port registers 1, 3 to 5, 14 (P1, P3 to P5, P14)).
• Timer clock select register m (TPSm)
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
2. Be sure to clear bits 1, 3, and 6 to “0”.
<R>