Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 181
Dec 13, 2013
Figure 6-4. Internal Block Diagram of Channel 3 of Timer Array Unit 0
TO03
CKS03CKS13 CCS03
SPLIT
03
STS032
STS031 STS030 MD032CIS031CIS030 MD033 MD031MD030
OVF
03
INTTM03
(Timer interrupt)
CK00
CK01
fMCK
f TCLK
CK02
CK03
INTTM03H
(Timer interrupt)
TI03
PMxx
Input signal from the master channel
Operating
clock selection
Interrupt
controller
Output
controller
Output latch
(Pxx)
Timer status
register 03 (TSR03)
Overflow
Timer data register 03 (TDR03)
Timer counter register 03 (TCR03)
Timer mode register 03 (TMR03)
Timer controller
Trigger
selection
Count clock
selection
Mode
selection
Edge
detection
Mode
selection
8-bit timer
controller
Interrupt
controller
Channel 3
Figure 6-5. Internal Block Diagram of Channel 5 of Timer Array Unit 0
Count clock
selection
TO05
PMxx
CKS05CKS15 CCS05 STS052STS051 STS050 MD052CIS051CIS050 MD053 MD051 MD050
OVF
05
INTTM05
(Timer interrupt)
CK00
CK01
f MCK
f TCLK
ISC1
RxD0
TI05
Input switch
control register
(ISC)
Interrupt
controller
Output
controller
Output latch
(Pxx)
Timer status
register 05 (TSR05)
Overflow
Timer data register 05 (TDR05)
Timer counter register 05 (TCR05)
Timer mode register 05 (TMR05)
Channel 5
Timer controller
Trigger
selection
Count clock
selection
Mode
selection
Edge
detection
Operating
clock selection
Input signal from the master channel
Selector
INTTM05H
(Timer interrupt)
Mode
selection
8-bit timer
controller
Interrupt
controller
<R>
<R>