Datasheet

RL78/L12 CHAPTER 5 CLOCK GENERATOR
R01UH0330EJ0200 Rev.2.00 137
Dec 13, 2013
5.3.2 System clock control register (CKC)
This register is used to select a CPU/peripheral hardware clock and main system clock.
The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 5-3. Format of System Clock Control Register (CKC)
Address: FFFA4H After reset: 00H R/W
Note 1
Symbol <7> <6> <5> <4> 3 2 1 0
CKC CLS CSS MCS MCM0 0 0 0 0
CLS Status of CPU/peripheral hardware clock (fCLK)
0 Main system clock (fMAIN)
1 Subsystem clock (fSUB)
CSS Selection of CPU/peripheral hardware clock (fCLK)
0 Main system clock (fMAIN)
1
Note 2
Subsystem clock (fSUB)
MCS Status of Main system clock (fMAIN)
0 High-speed on-chip oscillator clock (fIH)
1 High-speed system clock (fMX)
MCM0
Note
2
Main system clock (f
MAIN) operation control
0 Selects the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)
1 Selects the high-speed system clock (fMX) as the main system clock (fMAIN)
Notes 1. Bits 7 and 5 are read-only.
2. Changing the value of the MCM0 bit is prohibited while the CSS bit is set to 1.
Remarks 1. f
IH: High-speed on-chip oscillator clock frequency
f
MX: High-speed system clock frequency
f
MAIN: Main system clock frequency
fSUB: Subsystem clock frequency
2. ×: don’t care
Cautions 1. Be sure to set bit 3 to 0.
2. The clock set by the CSS bit is supplied to the CPU and peripheral hardware. If the
CPU clock is changed, therefore, the clock supplied to peripheral hardware (except
the real-time clock, 12-bit interval timer, clock output/buzzer output, LCD
driver/controller, and watchdog timer) is also changed at the same time.
Consequently, stop each peripheral function when changing the CPU/peripheral
hardware clock.
3. If the subsystem clock is used as the peripheral hardware clock, the operations of
the A/D converter and IICA are not guaranteed. For the operating characteristics of