Datasheet

RL78/L12 APPENDIX A REVISION HISTORY
R01UH0330EJ0200 Rev.2.00 981
Dec 13, 2013
(3/10)
Edition
Description Chapter
Rev.1.00
Modification of note 1 in Figure 6-12. Format of Timer Mode Register mn (TMRmn)
CHAPTER 6
TIMER ARRAY UNIT
Modification of Setting of starting counting and interrupt and addition of note 3 in Figure 6-12.
Format of Timer Mode Register mn (TMRmn) (4/4)
Modification of description in Figure 6-16. Format of Timer Channel Stop register m (TTm)
Addition of caution to Figure 6-17. Format of Timer Input Select register 0 (TIS0)
Modification of description in Figure 6-19. Format of Timer Output Enable register m (TOEm)
Modification of description in Table 6-6. Operations from Count Operation Enabled State to
Timer count Register mn (TCRmn) Count Start
Addition of title and remark to 6.5.3 Operation of counter
Modification of description, remark and addition note to Figure 6-30. Start Timing (In Capture
Mode : Input Pulse Interval Measurement)
Modification of description in 6.6.2 TOmn Pin Output Setting
Modification of Figures 6-35 to 6-37
Modification of Figures 6-47, 6-51, 6-55, 6-59, 6-63, 6-67 Block Diagram
Modification of remark in 6.8.3 Operation as multiple PWM output function
Modification of Figure 6-83. Procedure for Setting Remote control Output
Modification of 7.4.2 Shifting to HALT/STOP mode after starting operation
CHAPTER 7
REAL-TIME CLOCK
Modification of figure title in Figure 7-23
Modification of Figure 8-5. 12-bit Interval Timer Operation Timing (ITMCMP11 to ITMCMP0 =
0FFH, count clock: f
SUB = 32.768 kHz)
CHAPTER 8
INTERVAL TIMER
Addition of 9.3.3 Port mode registers 5, 14 (PM5, PM14)
CHAPTER 9
CLOCK
OUTPUT/BUZZER
OUTPUT
CONTROLLER
Addition of 9.5 Cautions of clock output/buzzer output controller
Modification of description in 10.1 Functions of Watchdog Timer, 10.4.4 Setting watchdog timer
interval interrupt
CHAPTER 10
WATCHDOG TIMER
Modification of Figure 11-1. Block Diagram of A/D Converter
CHAPTER 11
A/D CONVERTER
Modification of error in 11.2 (9) AVREFP pin
Modification of caution 1 in 11.3.1 Peripheral enable register 0 (PER0)
Modification of cautions 1 and 3 and addition of caution 2 in 11.3.2 A/D converter mode
register 0 (ADM0)
Modification of Table 11-1. Settings of ADCS and ADCE Bits
Modification of description and addition of note 2 and caution 4 to Figure 11-4. Timing Chart
When A/D Voltage Comparator Is Used
Modification of Table 11-3. A/D Conversion Time Selection
Modification of cautions 1, 2 and addition of caution 3 in 11.3.3 A/D converter mode register 1
(ADM1)