Datasheet

RL78/L12 CHAPTER 3 CPU ARCHITECTURE
R01UH0330EJ0200 Rev.2.00 70
Dec 13, 2013
Table 3-5. SFR List (2/4)
Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset
1-bit 8-bit 16-bit
FFF38H External interrupt rising edge enable
register 0
EGP0 R/W
√ √ −
00H
FFF39H External interrupt falling edge enable
register 0
EGN0 R/W
√ √ −
00H
FFF40H LCD mode register 0 LCDM0 R/W
− √ −
00H
FFF41H LCD mode register 1 LCDM1 R/W
√ √ −
00H
FFF42H LCD clock control register LCDC0 R/W
− √ −
00H
FFF43H LCD boost level control register VLCD R/W
− √ −
04H
FFF50H IICA shift register 0 IICA0 R/W
− √ −
00H
FFF51H IICA status register 0 IICS0 R
√ √ −
00H
FFF52H IICA flag register 0 IICF0 R/W
√ √ −
00H
FFF64H Timer data register 02 TDR02 R/W
− − √
0000H
FFF65H
FFF66H Timer data register 03 TDR03L TDR03 R/W
− √ √
00H
FFF67H TDR03H
− √
00H
FFF68H Timer data register 04 TDR04 R/W
− − √
0000H
FFF69H
FFF6AH Timer data register 05 TDR05 R/W
− − √
0000H
FFF6BH
FFF6CH Timer data register 06 TDR06 R/W
− − √
0000H
FFF6DH
FFF6EH Timer data register 07 TDR07 R/W
− − √
0000H
FFF6FH
FFF90H Interval timer control register ITMC R/W
− − √
0FFFH
FFF91H
FFF92H Second count register SEC
Note 2
R/W
− √ −
00H
FFF93H Minute count register MIN
Note 2
R/W
− √ −
00H
FFF94H Hour count register HOUR
Note 2
R/W
− √ −
12H
Note 1
FFF95H Week count register WEEK
Note 2
R/W
− √ −
00H
FFF96H Day count register DAY
Note 2
R/W
− √ −
01H
Notes 1. The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1
after reset.
2. 44-, 48-, 52-, and 64-pin product only