Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 458
Dec 13, 2013
(1) Register setting
Figure 12-61. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01) (1/2)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn
CKSmn
0/1
CCSmn
1 0 0 0 0 0
STSmn
0 0
SISmn0
0 1 0 0 0
MDmn1
0
MDmn0
0/1
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn
TXEmn
1
RXEmn
1
DAPmn
0/1
CKPmn
0/1 0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1 0
SLCmn1
0
SLCmn0
0 0 1
DLSmn1
1
DLSmn0
0/1
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
Setting of data length
0: 7-bit data length
1: 8-bit data length
Selection of the data and clock
phase (For details about the
setting, see 12.3 Registers
Controlling Serial Array Unit.)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
0000000
Baud rate setting
0
Transmit data setting/receive data register
(d) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0 0 0 0 1 1
CKOm1
×
CKOm0
×
0 0 0 0 1 1
SOm1
0/1
SOm0
0/1
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01), mn = 00, 01
2. : Setting is fixed in the CSI slave transmission/reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp