Datasheet

RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: T
A = -40 to +85°C)
R01UH0330EJ0200 Rev.2.00 896
Dec 13, 2013
(2) I
2
C fast mode
(T
A = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Conditions
HS (high-
speed main)
Mode
LS
(low-speed
main) Mode
LV (low-
voltage main)
Mode
Unit
MIN. MAX. MIN. MIN. MAX. MIN.
SCLA0 clock frequency fSCL
Fast mode:
f
CLK ≥ 3.5
MHz
2.7 V ≤ EV
DD ≤ 5.5 V 0 400 0 400 0 400 kHz
2.4 V ≤ EVDD ≤ 5.5 V 0 400 0 400 0 400
1.8 V ≤ EVDD ≤ 5.5 V 0 400 0 400
Setup time of restart condition tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6
1.8 V ≤ EVDD ≤ 5.5 V 0.6 0.6
Hold time
Note 1
tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6
1.8 V ≤ EVDD ≤ 5.5 V 0.6 0.6
Hold time when SCLA0 = “L” tLOW 2.7 V ≤ EVDD ≤ 5.5 V 1.3 1.3 1.3 μ s
2.4 V ≤ EVDD ≤ 5.5 V 1.3 1.3 1.3
1.8 V ≤ EVDD ≤ 5.5 V 1.3 1.3
Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6
1.8 V ≤ EVDD ≤ 5.5 V 0.6 0.6
Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 100 100 100 ns
2.4 V ≤ EVDD ≤ 5.5 V 100 100 100
1.8 V ≤ EVDD ≤ 5.5 V 100 100
Data hold time (transmission)
Note 2
tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 0.9 0 0.9 0 0.9 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0 0.9 0 0.9 0 0.9
1.8 V ≤ EVDD ≤ 5.5 V 0 0.9 0 0.9
Setup time of stop condition tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6
1.8 V ≤ EVDD ≤ 5.5 V 0.6 0.6
Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 1.3 1.3 1.3 μ s
2.4 V ≤ EVDD ≤ 5.5 V 1.3 1.3 1.3
1.8 V ≤ EVDD ≤ 5.5 V 1.3 1.3
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of t
HD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode: C
b = 320 pF, Rb = 1.1 kΩ
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