Datasheet

RL78/L12
CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
R01UH0330EJ0200 Rev.2.00 959
Dec 13, 2013
31.7.3 Capacitor split method
1/3 bias method
(T
A = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VL4 voltage VL4 C1 to C4 = 0.47 μ F
Note 2
VDD V
VL2 voltage VL2 C1 to C4 = 0.47 μ F
Note 2
2/3 VL4
− 0.1
2/3 V
L4 2/3 VL4
+ 0.1
V
VL1 voltage VL1 C1 to C4 = 0.47 μ F
Note 2
1/3 VL4
− 0.1
1/3 V
L4 1/3 VL4
+ 0.1
V
Capacitor split wait time
Note 1
tVWAIT 100 ms
Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
2. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between V
L1 and GND
C3: A capacitor connected between V
L2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
31.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.44
Note
5.5 V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR
reset is effected, but data is not retained when a POR reset is effected.
V DD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
Data retention mode
V
DDDR
Operation mode