Datasheet

RL78/L12
CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
R01UH0330EJ0200 Rev.2.00 943
Dec 13, 2013
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
DD tolerance (32- to 52-pin
products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For V
IH and VIL, see the DC
characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
SOp
SCK
SI
SIp
SO
V
b
Rb
<Master>
RL78
microcontroller
User's device
Remarks 1. R
b[Ω]:Communication line (SCKp, SOp) pull-up resistance,
C
b[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00))