Datasheet

RL78/L12 CHAPTER 3 CPU ARCHITECTURE
R01UH0330EJ0200 Rev.2.00 73
Dec 13, 2013
Table 3-5. SFR List (4/4)
Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset
1-bit 8-bit 16-bit
FFFD0H Interrupt request flag register 2L IF2L IF2 R/W
√ √ √
00H
FFFD4H Interrupt mask flag register 2L MK2L MK2 R/W
√ √ √
FFH
FFFD8H Priority specification flag register 02L PR02L PR02 R/W
√ √ √
FFH
FFFDCH Priority specification flag register 12L PR12L PR12 R/W
√ √ √
FFH
FFFE0H Interrupt request flag register 0L IF0L IF0 R/W
√ √ √
00H
FFFE1H Interrupt request flag register 0H IF0H R/W
√ √
00H
FFFE2H Interrupt request flag register 1L IF1L IF1 R/W
√ √ √
00H
FFFE3H Interrupt request flag register 1H IF1H R/W
√ √
00H
FFFE4H Interrupt mask flag register 0L MK0L MK0 R/W
√ √ √
FFH
FFFE5H Interrupt mask flag register 0H MK0H R/W
√ √
FFH
FFFE6H Interrupt mask flag register 1L MK1L MK1 R/W
√ √ √
FFH
FFFE7H Interrupt mask flag register 1H MK1H R/W
√ √
FFH
FFFE8H Priority specification flag register 00L PR00L PR00 R/W
√ √ √
FFH
FFFE9H Priority specification flag register 00H PR00H R/W
√ √
FFH
FFFEAH Priority specification flag register 01L PR01L PR01 R/W
√ √ √
FFH
FFFEBH Priority specification flag register 01H PR01H R/W
√ √
FFH
FFFECH Priority specification flag register 10L PR10L PR10 R/W
√ √ √
FFH
FFFEDH Priority specification flag register 10H PR10H R/W
√ √
FFH
FFFEEH Priority specification flag register 11L PR11L PR11 R/W
√ √ √
FFH
FFFEFH Priority specification flag register 11H PR11H R/W
√ √
FFH
FFFF0H Multiplication/division data register A (L) MDAL R/W
− − √
0000H
FFFF1H
FFFF2H Multiplication/division data register A (H) MDAH R/W
− − √
0000H
FFFF3H
FFFF4H Multiplication/division data register B (H) MDBH R/W
− − √
0000H
FFFF5H
FFFF6H Multiplication/division data register B (L) MDBL R/W
− − √
0000H
FFFF7H
FFFFEH Processor mode control register PMC R/W
√ √ −
00H
Remark For extended SFRs (2nd SFRs), see Table 3-6 Extended SFR (2nd SFR) List.