Datasheet

RL78/L12 CHAPTER 3 CPU ARCHITECTURE

R01UH0330EJ0200 Rev.2.00 72

Dec 13, 2013

Notes 1. The reset values of the registers vary depending on the reset source as shown below.

Reset Source

RESET Input

Reset by

POR

Reset by

Execution of

Illegal

Instruction

Reset by

WDT

Reset by

RAM parity

error

Reset by

illegal-

memory

access

Reset by

LVD

RESF TRAP bit Cleared (0) Set (1) Held Held

WDTRF bit Held Set (1) Held

RPERF bit Held Set (1) Held

IAWRF bit Held Set (1)

LVIRF bit Held Set (1)

LVIM LVISEN bit Cleared (0) Held

LVIOMSK bit Held

LVIF bit

LVIS Cleared (00H/01H/81H)

2. The reset value of the WDTE register is determined by the setting of the option byte.

3. 44-, 48-, 52-, and 64-pin product only

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