Datasheet
RL78/L12 CHAPTER 3 CPU ARCHITECTURE
R01UH0330EJ0200 Rev.2.00 71
Dec 13, 2013
Table 3-5. SFR List (3/4)
Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset
1-bit 8-bit 16-bit
FFF97H Month count register MONTH
Note 3
R/W
− √ −
01H
FFF98H Year count register YEAR
Note 3
R/W
− √ −
00H
FFF99H Watch error correction register SUBCUD
Note 3
R/W
− √ −
00H
FFF9AH Alarm minute register ALARMWM
Note 3
R/W
− √ −
00H
FFF9BH Alarm hour register ALARMWH
Note 3
R/W
− √ −
12H
FFF9CH Alarm week register ALARMWW
Note 3
R/W
− √ −
00H
FFF9DH Real-time clock control register 0 RTCC0 R/W
√ √ −
00H
FFF9EH Real-time clock control register 1 RTCC1
Note 3
R/W
√ √ −
00H
FFFA0H Clock operation mode control register CMC R/W
− √ −
00H
FFFA1H Clock operation status control register CSC R/W
√ √ −
C0H
FFFA2H Oscillation stabilization time counter
status register
OSTC R
√ √ −
00H
FFFA3H Oscillation stabilization time select
register
OSTS R/W
− √ −
07H
FFFA4H System clock control register CKC R/W
√ √ −
00H
FFFA5H Clock output select register 0 CKS0 R/W
√ √ −
00H
FFFA6H Clock output select register 1 CKS1
Note 3
R/W
√ √ −
00H
FFFA8H Reset control flag register RESF R
− √ −
Undefined
Note 1
FFFA9H Voltage detection register LVIM R/W
√ √ −
00H
Note 1
FFFAAH Voltage detection level register LVIS R/W
√ √ −
00H/01H/81H
Note 1
FFFABH Watchdog timer enable register WDTE R/W
− √ −
1AH/9AH
Note 2
FFFACH CRC input register CRCIN R/W
− √ −
00H
FFFB0H DMA SFR address register 0 DSA0 R/W
− √ −
00H
FFFB1H DMA SFR address register 1 DSA1 R/W
− √ −
00H
FFFB2H DMA RAM address register 0L DRA0L DRA0 R/W
− √ √
00H
FFFB3H DMA RAM address register 0H DRA0H R/W
− √
00H
FFFB4H DMA RAM address register 1L DRA1L DRA1 R/W
− √ √
00H
FFFB5H DMA RAM address register 1H DRA1H R/W
− √
00H
FFFB6H DMA byte count register 0L DBC0L DBC0 R/W
− √ √
00H
FFFB7H DMA byte count register 0H DBC0H R/W
− √
00H
FFFB8H DMA byte count register 1L DBC1L DBC1 R/W
− √ √
00H
FFFB9H DMA byte count register 1H DBC1H R/W
− √
00H
FFFBAH DMA mode control register 0 DMC0 R/W
√ √ −
00H
FFFBBH DMA mode control register 1 DMC1 R/W
√ √ −
00H
FFFBCH DMA operation control register 0 DRC0 R/W
√ √ −
00H
FFFBDH DMA operation control register 1 DRC1 R/W
√ √ −
00H
(Notes are listed on the next page.)
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