Datasheet

RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: T
A = -40 to +85°C)
R01UH0330EJ0200 Rev.2.00 894
Dec 13, 2013
30.5.2 Serial interface IICA
(1) I
2
C standard mode
(T
A = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Conditions
HS (high-
speed main)
Mode
LS
(low-speed
main) Mode
LV (low-
voltage main)
Mode
Unit
MIN. MAX. MIN. MIN. MAX. MIN.
SCLA0 clock frequency fSCL
Standard
mode:
f
CLK ≥ 1 MHz
2.7 V ≤ EV
DD ≤ 5.5 V 0 100 0 100 0 100 kHz
2.4 V ≤ EVDD ≤ 5.5 V 0 100 0 100 0 100
1.8 V ≤ EVDD ≤ 5.5 V 0 100 0 100
1.6 V ≤ EVDD ≤ 5.5 V 0 100
Setup time of restart condition tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7
1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7
1.6 V ≤ EVDD ≤ 5.5 V 4.7
Hold time
Note 1
tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0
1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0
1.6 V ≤ EVDD ≤ 5.5 V 4.0
Hold time when SCLA0 = “L” tLOW 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7
1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7
1.6 V ≤ EVDD ≤ 5.5 V 4.7
Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0
1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0
1.6 V ≤ EVDD ≤ 5.5 V 4.0
Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 250 250 250 ns
2.4 V ≤ EVDD ≤ 5.5 V 250 250 250
1.8 V ≤ EVDD ≤ 5.5 V 250 250
1.6 V ≤ EVDD ≤ 5.5 V 250
Data hold time (transmission)
Note 2
tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45
1.8 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45
1.6 V ≤ EVDD ≤ 5.5 V 0 3.45
Setup time of stop condition tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0
1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0
1.6 V ≤ EVDD ≤ 5.5 V 4.0
Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7
1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7
1.6 V ≤ EVDD ≤ 5.5 V 4.7
(Notes and Remark are listed on the next page.)
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