Datasheet

RL78/L12 CHAPTER 22 VOLTAGE DETECTOR
R01UH0330EJ0200 Rev.2.00 769
Dec 13, 2013
22.4.3 When used as interrupt and reset mode
• When starting operation
Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage
(V
LVDH, VLVDL) by using the option byte 000C1H.
Start in the following initial setting state.
• Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level
register (LVIS)).
• When the option byte LVIMDS1 is set to 1 and LVIMDS0 is cleared to 0, the initial value of the LVIS register is
set to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 0 (low-voltage detection level: V
LVDH).
Figure 22-6 shows the timing of the internal reset signal and interrupt signal generated by the voltage detector.
Perform the processing according to Figure 22-7 Processing Procedure After an Interrupt is Generated.
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