Datasheet

RL78/L12 CHAPTER 21 POWER-ON-RESET CIRCUIT
R01UH0330EJ0200 Rev.2.00 758
Dec 13, 2013
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
and Voltage Detector (3/3)
(3) LVD reset mode (option byte 000C1H: LVIMDS1 = 1, LVIMDS0 = 1)
0 V
V LVD
V POR = 1.51 V (TYP.)
V
PDR = 1.50 V (TYP.)
Lower limit voltage for guaranteed operation
Supply voltage (V
DD )
Reset period
(oscillation
stop)
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
Normal operation
(high-speed on-chip
oscillator clock)
Note 2
Normal operation
(high-speed on-chip
oscillator clock)
Note 2
Normal operation
(high-speed on-chip
oscillator clock)
Note 2
LVD reset processing
time
Note 3
LVD reset processing
time
Note 4
LVD reset processing
time
Note 3
Note 1
Wait for oscillation
accuracy stabilization
Note 1
Wait for oscillation
accuracy stabilization
Note 1
Starting oscillation
is specified by software
Starting oscillation
is specified by software
Starting oscillation
is specified by software
Internal reset signal
CPU Operation stops
High-speed
system clock (f
MX )
(when X1 oscillation
is selected)
High-speed on-chip
oscillator clock (f
IH )
Voltage stabilization wait + POR reset processing time
1.64 ms (TYP.), 3.10 ms (MAX.)
Operation stops
Voltage stabilization wait + POR reset processing time
1.64 ms (TYP.), 3.10 ms (MAX.)
Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-
chip oscillator clock.
2. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected
as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC)
to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for
confirmation of the lapse of the stabilization time.
3. The time until normal operation starts includes the following LVD reset processing time after the LVD
detection level (V
LVD) is reached as well as the voltage stabilization wait + POR reset processing time after
the V
POR (1.51 V, typ.) is reached.
LVD reset processing time: 0 ms to 0.0701 ms (max.)
4. When the power supply voltage is below the lower limit for operation and the power supply voltage is then
restored after an internal reset is generated only by the voltage detector (LVD), the following LVD reset
processing time is required after the LVD detection level (V
LVD) is reached.
LVD reset processing time: 0.0511 ms (typ.), 0.0701 ms (max.)
Remark V
POR: POR power supply rise detection voltage
V
PDR: POR power supply fall detection voltage
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