Datasheet

RL78/L12 CHAPTER 20 RESET FUNCTION

R01UH0330EJ0200 Rev.2.00 752

Dec 13, 2013

The status of the RESF register when a reset request is generated is shown in Table 20-3.

Table 20-3. RESF Register Status When Reset Request Is Generated

Reset Source

Flag

RESET Input

Reset by

POR

Reset by

Execution of

Illegal

Instruction

Reset by

WDT

Reset by

RAM parity

error

Reset by

illegal-

memory

access

Reset by

LVD

TRAP bit Cleared (0) Cleared (0) Set (1) Held Held Held Held

WDTRF bit Held Set (1)

RPERF bit Held Set (1)

IAWRF bit Held Set (1)

LVIRF bit Held Set (1)

The RESF register is automatically cleared when it is read by an 8-bit memory manipulation instruction. Figure 20-5

shows the procedure for checking a reset source.

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