Datasheet

RL78/L12 CHAPTER 20 RESET FUNCTION
R01UH0330EJ0200 Rev.2.00 749
Dec 13, 2013
20.2 States of Operation During Reset Periods
Table 20-1 shows the states of operation during reset periods. Table 20-2 shows the states of the hardware after
receiving a reset signal.
Table 20-1. States of Operation During Reset Period
Item During Reset Period
System clock Clock supply to the CPU is stopped.
Main system clock fIH Operation stopped
fX Operation stopped (the X1 and X2 pins are input port mode)
fEX Clock input invalid (the pin is input port mode)
Subsystem clock fXT Operation stopped (the XT1 and XT2 pins are input port mode)
fEXS Clock input invalid (the pin is input port mode)
fIL Operation stopped
CPU Operation stopped
Code flash memory Operation stopped
Data flash memory Operation stopped
RAM Operation stopped
Port (latch) High impedance
Note
Timer array unit Operation stopped
Real-time clock (RTC)
12-bit interval timer
Watchdog timer
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface (IICA)
LCD controller/driver Operation stopped
(COM only pin, COM/SEG alternate pin: GND output,
SEG/general-purpose port alternate pin: high-impedance output,
V
L1 to VL4 pins: high-impedance output,
CAPH/P127 pin, CAPL/P126 pin: high-impedance output)
Multiplier & divider, multiply-
accumulator
Operation stopped
DMA controller
Power-on-reset function Detection operation possible
Voltage detection function Operation stopped
External interrupt Operation stopped
Key interrupt function
CRC
operation
function
High-speed CRC
General-purpose CRC
RAM parity error detection function
RAM guard function
SFR guard function
Illegal-memory access detection
function
(Note and Remark are listed on the next page.)
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